參數(shù)資料
型號: PCF8584
廠商: NXP Semiconductors N.V.
英文描述: IIC-bus controller(IIC總線控制器)
中文描述: IIC總線控制器(國際進(jìn)口總線控制器)
文件頁數(shù): 5/40頁
文件大?。?/td> 224K
代理商: PCF8584
1997 Oct 21
5
Philips Semiconductors
Product specification
I
2
C-bus controller
PCF8584
5
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
CLK
SDA or
SDA OUT
SCL or SCL IN
IACK or
SDA IN
1
2
I
clock input from microcontroller clock generator (internal pull-up)
I
2
C-bus serial data input/output (open-drain). Serial data output in long-distance
mode.
I
2
C-serial clock input/output (open-drain). Serial clock input in long-distance mode.
Interrupt acknowledge input (internal pull-up); when this signal is asserted the
interrupt vector in register S3 will be available at the bus Port if the ENI flag is set.
Serial data input in long-distance mode.
Interrupt output (open-drain); this signal is enabled by the ENI flag in register S1.
It is asserted when the PIN flag is reset. (PIN is reset after 1 byte is transmitted or
received over the I
2
C-bus). Serial clock output in long-distance mode.
Register select input (internal pull-up); this input selects between the control/status
register and the other registers. Logic 1 selects register S1, logic 0 selects one of
the other registers depending on bits loaded in ESO, ES1 and ES2 of register S1.
bidirectional 8-bit bus Port 0
bidirectional 8-bit bus Port 1
bidirectional 8-bit bus Port 2
ground
bidirectional 8-bit bus Port 3
bidirectional 8-bit bus Port 4
bidirectional 8-bit bus Port 5
bidirectional 8-bit bus Port 6
bidirectional 8-bit bus Port 7
RD is the read control input for MAB8049, MAB8051 or Z80-types. DTACK is the
data transfer control output for 68000-types (open-drain).
chip select input (internal pull-up)
WR is the write control input for MAB8048, MAB8051, or Z80-types
(internal pull-up). R/W control input for 68000-types.
Reset input (open-drain); this input forces the I
2
C-bus controller into a predefined
state; all flags are reset, except PIN, which is set. Also functions as strobe output.
supply voltage
I/O
3
4
I/O
I
INT or
SCL OUT
5
O
A0
6
I
DB0
DB1
DB2
V
SS
DB3
DB4
DB5
DB6
DB7
RD (DTACK)
7
8
9
10
11
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/(O)
CS
WR (R/W)
17
18
I
I
RESET/
STROBE
V
DD
19
I/O
20
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