參數(shù)資料
型號(hào)： PCF8584
廠商： NXP Semiconductors N.V.
英文描述： IIC-bus controller(IIC總線控制器)
中文描述： IIC總線控制器（國(guó)際進(jìn)口總線控制器）
文件頁(yè)數(shù)： 11/40頁(yè)
文件大?。?/td> 224K
代理商： PCF8584
1997 Oct 21
11
Philips Semiconductors
Product specification
I
2
C-bus controller
PCF8584
6.8.1.5
STA and STO
These bits control the generation of the I
2
C-bus START condition and transmission of slave address and R/W bit,
generation of repeated START condition, and generation of the STOP condition (see Table 7).
Table 6
Register access control; ESO = 1 (serial interface on) and ES1 = 1; long-distance (4-wire) mode; note 1
Note
1.
Trying to read from or write to registers other than S0 and S1 (setting ESO = 0) brings the PCF8584 out of the
long-distance mode.
Table 7
Instruction table for serial bus control
Notes
1.
2.
In master receiver mode, the last byte must be terminated with ACK bit HIGH (‘negative acknowledge’).
If both STA and STO are set HIGH simultaneously in master mode, a STOP condition followed by a START
condition + address will be generated. This allows ‘chaining’ of transmissions without relinquishing bus control.
All other STA and STO mode combinations not mentioned in Table 7 are NOPs.
3.
6.8.1.6
ACK
This bit must be set normally to a logic 1. This causes the I
2
C-bus controller to send an acknowledge automatically after
each byte (this occurs during the 9th clock pulse). The bit must be reset (to logic 0) when the I
2
C-bus controller is
operating in master/receiver mode and requires no further data to be sent from the slave transmitter. This causes a
negative acknowledge on the I
2
C-bus, which halts further transmission from the slave device.
6.8.2
R
EGISTER
S1
STATUS SECTION
The read-only section of S1 enables access to I
2
C-bus status information; see Table 4.
INTERNAL REGISTER ADDRESSING: LONG-DISTANCE (4-WIRE) MODE
A0
ES1
ES2
IACK
FUNCTION
1
1
0
1
1
1
X
X
X
1
X
X
W S1: control
R S1; status
R/W S0; (data)
STA
STO
PRESENT
MODE
FUNCTION
OPERATION
1
0
SLV/REC
START
transmit START + address, remain
MST/TRM if R/W = 0;
go to MST/REC if R/W = 1
same as for SLV/REC
1
0
MST/TRM
REPEAT
START
STOP READ;
STOP WRITE
DATA
CHAINING
NOP
0
1
MST/REC;
MST/TRM
MST
transmit STOP go to SLV/REC mode; note 1
1
1
send STOP, START and address after last
master frame without STOP sent; note 2
no operation; note 3
0
0
ANY
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