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參數(shù)資料
| 型號(hào)： | PCF8584 |
| 廠(chǎng)商： | NXP Semiconductors N.V. |
| 英文描述： | IIC-bus controller(IIC總線(xiàn)控制器) |
| 中文描述： | IIC總線(xiàn)控制器（國(guó)際進(jìn)口總線(xiàn)控制器） |
| 文件頁(yè)數(shù)： | 24/40頁(yè) |
| 文件大?。?/td> | 224K |
| 代理商： | PCF8584 |
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1997 Oct 21
24
Philips Semiconductors
Product specification
I
2
C-bus controller
PCF8584
12 I
2
C-BUS TIMING SPECIFICATIONS
All the timing limits are valid within the operating supply voltage and ambient temperature range; V
DD
= 5 V
±
10%;
T
amb
=
40 to +85
°
C; and refer to V
IL
and V
IH
with an input voltage of V
SS
to V
DD.
13 PARALLEL INTERFACE TIMING
All the timing limits are valid within the operating supply voltage and ambient temperature range: V
DD
= 5 V
±
10%;
T
amb
=
40 to +85
°
C; and refer to V
IL
and V
IH
with an input voltage of V
SS
to V
DD
. C
L
= 100 pF; R
L
= 1.5 k
(connected to V
DD
) for open-drain and high-impedance outputs, where applicable (for measurement purposes only).
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
f
SCL
t
SW
t
BUF
t
SU;STA
t
HD;STA
t
LOW
t
HIGH
t
r
t
f
t
SU;DAT
t
HD;DAT
t
VD;DAT
t
SU;STO
SCL clock frequency
tolerable spike width on bus
bus free time
START condition set-up time
START condition hold time
SCL LOW time
SCL HIGH time
SCL and SDA rise time
SCL and SDA fall time
data set-up time
data hold time
SCL LOW to data out valid
STOP condition set-up time
4.7
4.7
4.0
4.7
4.0
250
0
4.0
100
100
1.0
0.3
3.4
kHz
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
μ
s
μ
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
t
r
t
f
t
CLK
clock rise time
clock fall time
input clock period
(50%
±
5% duty factor)
CS set-up to RD LOW
CS set-up to WR LOW
CS hold from RD HIGH
CS hold from WR HIGH
A0 set-up to WR LOW
A0 set-up to RD LOW
A0 hold from WR HIGH
A0 hold from RD HIGH
WR pulse width
RD pulse width
data set-up before WR HIGH
data valid after RD LOW
data hold after WR HIGH
data bus floating after RD
HIGH
see Fig.14
see Fig.14
see Fig.14
83
6
6
333
ns
ns
ns
t
CLRL
t
CLWL
t
RHCH
t
WHCH
t
AVWL
t
AVRL
t
WHAI
t
RHAI
t
WLWH
t
RLRH
t
DVWH
t
RLDV
t
WHDI
t
RHDF
see Fig.16 and note 1 20
see Fig.15 and note 1 20
see Fig.16
see Fig.15
see Fig.15
see Fig.16
see Fig.15
see Fig.16
see Fig.15
see Fig.16
see Fig.15
see Fig.16
see Fig.15
see Fig.16
160
1000
1000
180
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
10
10
20
10
230
230
150
20
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