參數(shù)資料
型號: PCF8563
廠商: NXP Semiconductors N.V.
英文描述: Real-time clock/calendar(實時時鐘/日歷)
中文描述: 實時時鐘/日歷(實時時鐘/日歷)
文件頁數(shù): 6/30頁
文件大?。?/td> 676K
代理商: PCF8563
Philips Semiconductors
PCF8563
Real-time clock/calendar
Product specification
16 April 1999
6 of 30
9397 750 04855
Philips Electronics N.V. 1999. All rights reserved.
[1]
Not coded in BCD.
8.6.1
Control/Status 1 register
Table 5:
Bit positions labelled as ‘
’are not implemented.
Address Register name BCD format tens nibble
BCD formatted registers overview
BCD format units nibble
Bit 3
2
3
<seconds 00 to 59 coded in BCD>
<minutes 00 to 59 coded in BCD>
<hours 00 to 23 coded in BCD>
<days 01 to 31 coded in BCD>
<months 01 to 12 coded in BCD>
<years 00 to 99 coded in BCD>
<minute alarm 00 to 59 coded in BCD>
<hour alarm 00 to 23 coded in BCD>
<day alarm 01 to 31 coded in BCD>
Bit 7
2
3
VL
C
Bit 6
2
2
Bit 5
2
1
Bit 4
2
0
Bit 2
2
2
Bit 1
2
1
Bit 0
2
0
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
Seconds
Minutes
Hours
Days
Weekdays
Months/Century
Years
Minute alarm
Hour alarm
Day alarm
Weekday alarm
<weekdays 0 to 6 >
[1]
AE
AE
AE
AE
<weekday alarm 0 to 6 >
[1]
Table 6:
Bit
7
Control/Status 1 register bits description (address 00H)
Symbol Description
TEST1
TEST1 = 0; normal mode.
TEST1 = 1; EXT_CLK test mode; see
Section 8.7
.
STOP
STOP = 0; RTC source clock runs.
STOP = 1; all RTC divider chain flip-flops are asynchronously set
to logic 0; the RTC clock is stopped (CLKOUT at 32.768 kHz is still
available).
TESTC
TESTC = 0; power-on reset override facility is disabled (set to logic 0
for normal operation).
TESTC = 1; power-on reset override is enabled.
6, 4, 2 to 0 0
By default set to logic 0.
5
3
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