參數(shù)資料
型號(hào): PCF8563
廠商: NXP Semiconductors N.V.
英文描述: Real-time clock/calendar(實(shí)時(shí)時(shí)鐘/日歷)
中文描述: 實(shí)時(shí)時(shí)鐘/日歷(實(shí)時(shí)時(shí)鐘/日歷)
文件頁(yè)數(shù): 19/30頁(yè)
文件大?。?/td> 676K
代理商: PCF8563
Philips Semiconductors
PCF8563
Real-time clock/calendar
Product specification
16 April 1999
19 of 30
9397 750 04855
Philips Electronics N.V. 1999. All rights reserved.
11. Dynamic characteristics
[1]
[2]
Unspecified for f
CLKOUT
= 32.768 kHz.
All timing values are valid within the operating supply voltage range at T
amb
and referenced to V
IL
and V
IH
with an input voltage swing of
V
SS
to V
DD
.
I
2
C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
[3]
Table 30: Dynamic characteristics
V
DD
= 1.8 to 5.5 V; V
SS
= 0 V; T
amb
=
40 to +85
°
C; f
OSC
= 32.768 kHz; quartz R
s
= 40 k
; C
L
= 8 pF; unless otherwise
specified.
Symbol
Parameter
Conditions
Oscillator
C
L(integrated)
integrated load capacitance
f
OSC
/f
OSC
oscillator stability
V
DD
= 200 mV; T
amb
= 25
°
C
Quartz crystal parameters (f
OSC
= 32.768 kHz)
R
s
series resistance
C
L
parallel load capacitance
C
T
trimmer capacitance
CLKOUT output
δ
CLKOUT
CLKOUT duty factor
I
2
C-bus timing characteristics
[2]
f
SCL
SCL clock frequency
t
HD;STA
START condition hold time
t
SU;STA
set-up time for a repeated
START condition
t
LOW
SCL LOW time
t
HIGH
SCL HIGH time
t
r
SCL and SDA rise time
t
f
SCL and SDA fall time
C
b
capacitive bus line load
t
SU;DAT
data set-up time
t
HD;DAT
data hold time
t
SU;STO
set-up time for STOP condition
t
SW
tolerable spike width on bus
Min
Typ
Max
Unit
15
25
2
×
10
7
35
pF
5
10
40
25
k
pF
pF
[1]
50
%
[3]
400
kHz
μ
s
μ
s
0.6
0.6
1.3
0.6
100
0
4.0
0.3
0.3
400
50
μ
s
μ
s
μ
s
μ
s
pF
ns
ns
μ
s
ns
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