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參數(shù)資料
| 型號： | PCF2042V |
| 元件分類： | DRAM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大小： | 264K |
| 代理商： | PCF2042V |
1997 Feb 03
9
Philips Semiconductors
Product Specification
Memory card IC
PCF2042 V2
5.2
Clock
The frequency delivered by the IFD on CLK shall be in the
range of 7 kHz to 50 kHz with a duty cycle between 40%
and 60%. When switching frequencies, no pulse shall be
shorter than 40% of the shorter period.
5.3
Command format
Each command consists of three bytes. The first byte
(Control byte) defines the command to be executed. The
second one defines the address in the EEPROM memory
and the third one contains the Data byte.
Table 1
The LSB of transmitted bytes is always send first.
Command format
Table 2
The control byte is coded according to the table below.
Coding of commands
Any faulty input condition from IFD to IC will force the following response after the stop condition:
the IC responds with processing mode,
the IC sets I/O to HIGH after 8 falling edges of CLK.
CONTROL BYTE
BYTE ADDRESS
DATA BYTE
MSB
LSB MSB
LSB MSB
LSB
CONTROL
BYTE
BYTE
ADDRESS
DATA BYTE
COMMAND
MODE
MSB / LSB
0011.0000
0011.0001
0011.0010
0011.0011
0011.0100
0011.0101
0011.0110
0011.0111
0011.1000
0011.1001
0011.1010
0011.1011
0011.1100
0011.1101
0011.1110
0011.1111
0x00-0xFF
xx
--
0x01-0x03
xx
--
--
--
0x00-0xFF
0x00-0x03
--
--
0x00-0x1F
--
--
--
xx
xx
--
READ MAIN MEMORY
READ SECURITY MEMORY
not defined
COMPARE VERIFICATION DATA
READ PROTECTION MEMORY
not defined
not defined
not defined
UPDATE MAIN MEMORY
UPDATE SECURITY MEMORY
not defined
not defined
WRITE PROTECTION MEMORY
not defined
not defined
not defined
outgoing
outgoing
processing
processing
outgoing
processing
processing
processing
processing
processing
processing
processing
processing
processing
processing
processing
byte 1-3
xx
--
--
--
data byte
data byte
--
--
data byte
--
--
--
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