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參數(shù)資料
| 型號： | PCF2042V |
| 元件分類： | DRAM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大小： | 264K |
| 代理商： | PCF2042V |
1997 Feb 03
7
Philips Semiconductors
Product Specification
Memory card IC
PCF2042 V2
5.1.2
C
OMMAND
M
ODE
- IFD
TO
IC
Any bit sequence transmitted from the interface device
(IFD) to the IC is embedded between a START condition
and a STOP condition:
START condition:
falling edge on I/O during CLK is HIGH
STOP condition:
rising edge on I/O during CLK is HIGH
Between the last bit of a bit sequence transmitted from IFD
to IC and the STOP condition, an additional clock pulse is
mandatory in order to set I/O to HIGH.
If not exactly 24 bits are transmitted from IFD, the IC
responds with processing mode.
Fig.4 The command phase.
5.1.3
O
UTGOING
D
ATA
/P
ROCESSING
M
ODE
- IC
TO
IFD
After the transmission of a bit sequence from interface
device (IFD) to IC, two operational modes of the IC are to
be distinguished.
5.1.3.1
Processing Mode
In this mode the IC is processing internally. No data bits
are sent.
During processing the IC has to be clocked continuously
by the IFD. In this phase the I/O is set to LOW by the IC.
The IC signals the end of its internal processing by
setting I/O to HIGH.
The IC discards any START/STOP condition during
processing mode.
Any further clock that follows when processing mode is
completed will not change the level on I/O.
The IC only indicates the ‘End of Processing’ to the IFD.
The IC provides no information about the result of the
‘processing’.
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