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參數(shù)資料
| 型號： | PCF2042V |
| 元件分類： | DRAM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 264K |
| 代理商： | PCF2042V |
1997 Feb 03
6
Philips Semiconductors
Product Specification
Memory card IC
PCF2042 V2
5.1
Transmission Protocol
The transmission protocol is a two-wire link protocol and is
identical to the protocol type S=10 for synchronous
transmission. The characteristics of synchronous
transmission are part of ISO 7816-3.
All data changes on I/O are initiated by the falling edge of
CLK.
5.1.1
R
ESET AND
A
NSWER
-
TO
-R
ESET
(ATR)
Reset of the IC complies with the synchronous parts of ISO
7816-3. The RESET can be given at any time during
operation. The first 32 clock pulses will provide the
Answer-to-Reset. (For details see Chapter 7.)
The IC discards any START/STOP condition during ATR.
After having read the last bit an additional clock pulse is
mandatory in order to set I/O to HIGH.
Any further clock that follows now will not change the level
on I/O.
Fig.3 The activation, RESET and Answer-To-Reset phase.
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