參數(shù)資料
型號(hào): PCF2042V
元件分類: DRAM
英文描述: EEPROM
中文描述: EEPROM的
文件頁數(shù): 10/22頁
文件大?。?/td> 264K
代理商: PCF2042V
1997 Feb 03
10
Philips Semiconductors
Product Specification
Memory card IC
PCF2042 V2
5.4
Description of Commands
5.4.1
R
EAD
M
AIN
M
EMORY
The READ MAIN MEMORY command reads out the
content of the Main Memory starting at the given byte
address up to the end of the memory (address 255). The
read access to the Main Memory is always possible.
5.4.2
R
EAD
P
ROTECTION
M
EMORY
The READ PROTECTION MEMORY command reads out
the Protection Memory starting at address 0x00 up to the
end of the memory (address 0x03). The read access to the
Protection Memory is always possible.
5.4.3
R
EAD
S
ECURITY
M
EMORY
The READ SECURITY MEMORY command reads out the
Security Memory starting at address 0x00 up to the end of
the memory (address 0x03). The read access to the
Security Memory is always possible.
The actual value of the Reference Data can only be read
after a ‘Write Access procedure’ has been carried out
successfully. Otherwise the Reference Data are
superseded by 0x00.
5.4.4
C
OMPARE
V
ERIFICATION
D
ATA
The purpose of this command is to achieve write access to
all three memories, the Protection Memory, the Security
Memory and the Main Memory.
Verification Data will be sent to the IC being internally
compared with the Reference Data. Furthermore, the
COMPARE VERIFICATION DATA command must be
used together with the Error Counter byte within the ‘Write
Access Procedure’ (see Fig.6).
As long as the full write access to the system is not given,
the content of the Error Counter can only be changed from
HIGH to LOW. Thus, single bit changes of the Error
Counter allow at three attempts to achieve the full write
access to the system using the ‘Write Access Procedure’.
If the ‘Write Access Procedure’ ends successfully, full write
access to the Error Counter is given also.
To achieve the full write access, first the Error Counter at
address 0x00 has to be written. Subsequently, all three
Reference Data bytes (Security Memory address:
0x01,0x02,0x03) have to be addressed using the
COMPARE VERIFICATION DATA command in the
sequence of increasing addresses starting with Reference
Data byte 1. Any command given in between these three
COMPARE VERIFICATION DATA commands will result in
a failure of the ‘Write Access Procedure’.
Any single COMPARE VERIFICATION DATA command
with mismatching byte between Verification and
Reference Data will abort the ‘Write Access Procedure’.
Failing the ‘Write Access Procedure’ when all three bits of
the Error Counter are LOW will forever disable any further
write access.
If wrong addresses (undefined or not-ascending) of the
Reference Data bytes or Error Counter are transmitted,
the ‘Write Access Procedure’ will fail.
The Data byte transmitted to set the Error Counter byte
shall only initiate transitions from HIGH to LOW of the Error
Counter bits. Otherwise the ‘Write Access Procedure’ fails.
If not exactly 24 bits are transmitted from IFD, the IC
responds with processing mode and the ‘Write Access
Procedure’ fails.
The number of clock cycles has to be identical for
successful/failing COMPARE VERIFICATION DATA
command.
A granted write access gets only disabled by a Power-off /
Power-on sequence.
Note:
On successful completion of the “Write Access Procedure”
the Error Counter should be reset by the IFD to ensure
again three attempts after another Power-off/Power-on
sequence.
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