參數(shù)資料
型號(hào)： PC107AMGHU100LD
廠商： ATMEL CORP
元件分類： 外設(shè)及接口
英文描述： PCI Bridge Memory Controller
中文描述： MULTIFUNCTION PERIPHERAL, CBGA503
封裝： 33 X 33 MM, HITCE, CERAMIC, BGA-503
文件頁(yè)數(shù)： 42/50頁(yè)
文件大?。?/td> 453K
代理商： PC107AMGHU100LD
42
PC107A [Preliminary]
2137C–HIREL–03/04
System Design
Information
PLL Power Supply
Filtering
The AV
DD
and LAV
DD
power signals are provided on the PC107A to provide power to the
peripheral logic/memory bus PLL and the SDRAM clock delay-locked loop (DLL),
respectively. To ensure stability of the internal clocks, the power supplied to the AV
DD
and LAV
DD
input signals should be filtered of any noise in the 500 kHz to 10 MHz reso-
nant frequency range of the PLLs. A separate circuit similar to the one shown in Figure
30 using surface mount capacitors with minimum effective series inductance (ESL) is
recommended for each of the AV
DD
and LAV
DD
power signal pins. Consistent with the
recommendations of Dr. Howard Johnson in
High Speed Digital Design: A Handbook of
Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recom-
mended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to
minimize noise coupled from nearby circuits. Routing directly as possible from the
capacitors to the input signal pins with minimal inductance of vias is important but pro-
portionately less critical for the LAV
DD
pin.
Figure 30.
PLL Power Supply Filter Circuit
Power Supply Voltage
Sequencing
The notes in Table 3 on page 12 contain cautions illustrated in Figure 3 on page 13
about the sequencing of the external bus voltages and internal voltages of the PC107A.
These cautions are necessary for the long term reliability of the part. If they are violated,
the electrostatic discharge (ESD) protection diodes will be forward biased and excessive
current can flow through these diodes. Figure 3 shows a typical ramping voltage
sequence where the DC power sources (voltage regulators and/or power supplies) are
connected as shown in Figure 31. The voltage regulator delay shown in Figure 3 can be
zero if the various DC voltage levels are all applied to the target board at the same time.
The ramping voltage sequence shows a scenario in which the V
DD
/AV
DD
/LAV
DD
power
plane is not loaded as much as the OV
DD
/GV
DD
power plane and thus V
DD
/AV
DD
/LAV
DD
ramps at a faster rate than OV
DD
/GV
DD
.
If the system power supply design does not control the voltage sequencing, the circuit of
Figure 31 can be added to meet these requirements. The MUR420 diodes of Figure 31
control the maximum potential difference between the 3.3 bus and internal voltages on
power-up and the 1N5820 Schottky diodes regulate the maximum potential difference
on power-down.
Vdd
AVdd or LAVdd
10
2.2
μ
F
2.2
μ
F
GND
Low ESL surface mount capacitors
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PC107AMZFU100L 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller
PC107AMZFU100LC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller
PC107AMZFU100LD 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller
PC107AVGHU100L 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller
PC107AVGHU100LC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller
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