參數(shù)資料
型號(hào): PC107AMGHU100LD
廠(chǎng)商: ATMEL CORP
元件分類(lèi): 外設(shè)及接口
英文描述: PCI Bridge Memory Controller
中文描述: MULTIFUNCTION PERIPHERAL, CBGA503
封裝: 33 X 33 MM, HITCE, CERAMIC, BGA-503
文件頁(yè)數(shù): 25/50頁(yè)
文件大小: 453K
代理商: PC107AMGHU100LD
25
PC107A [Preliminary]
2137C–HIREL–03/04
Figure 12.
DLL Locking Range Loop Delay (DLL_Standard = 1)
Operating Frequency
This section provides the AC electrical characteristics for the PC107A. After fabrication,
functional parts are sorted by maximum core frequency as shown in Figure 10 and
“Clock AC Specifications” on page 23 and tested for conformance to the AC specifica-
tions for that frequency. The core frequency is determined by the bus (PCI_SYNC_IN)
clock frequency and the settings of the PLL_CFG[0
3] signals. Parts are sold by maxi-
mum processor core frequency; see “Ordering Information” on page 46.
Table 10 provides the operating frequency information for the PC107A.
At recommended operating conditions (see Table 3 on page 12) with
LV
DD
= 3.3
±
0.3V.
Note:
1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0–3] settings must be chosen
such that the resulting peripheral logic/memory bus frequency, CPU (core) frequency,
and PLL (VCO) frequencies do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0–3] signal description in “Clock Rela-
tionships Choice” on page 41 for valid PLL_CFG[0–3] settings and PCI_SYNC_IN
frequencies.
0
5
10
15
20
25
30
35
40
0
5
10
15
45
50
Tloop Propagation Delay Time (ns)
Tclk = 0.9 x Tloop + 13.95 ns
T
Tclk = 0.45 x Tloop + 6.98 ns
Tclk = 0.55 x Tloop + 2.97 ns
Tclk = 1.1 x Tloop + 5.94 ns
Table 10.
Operating Frequency
Characteristic
(1)
66 MHz
100 MHz
Unit
Min
Max
Min
Max
Core (memory bus/processor bus) frequency
25
66
25
100
MHz
PCI input frequency (PCI_SYNC_IN)
12.5 – 66
MHz
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