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參數(shù)資料
| 型號： | PC107AMGHU100LD |
| 廠商： | ATMEL CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PCI Bridge Memory Controller |
| 中文描述： | MULTIFUNCTION PERIPHERAL, CBGA503 |
| 封裝： | 33 X 33 MM, HITCE, CERAMIC, BGA-503 |
| 文件頁數(shù)： | 31/50頁 |
| 文件大?。?/td> | 453K |
| 代理商： | PC107AMGHU100LD |
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31
PC107A [Preliminary]
2137C–HIREL–03/04
Two-wire Interface AC Timing
Specifications
Table 14 provides the two-wire interface input AC timing specifications for the PC107A.
At recommended operating conditions (see Table 3 on page 12) with
LV
DD
= 3.3
±
0.3V
Notes:
1. Units for these specifications are in SDRAM_CLK/CPU_CLK units.
2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency
Divider Register two-wire interface FDR. Therefore, the noted timings in the above table are all relative to qualified signals.
The qualified SCL and SDA are delayed signals from what is seen in real time on the two-wire interface bus. The qualified
SCL, SDA signals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK/CPU_CLK
clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 19 on page 34.
3. Timing is relative to the Sampling Clock (not SCL).
4. FDR[x] refers to the Frequency Divider Register I2CFDR bit x.
5. Input clock low and high periods in combination with the FDR value in the Frequency Divider Register (I2CFDR) determine
the maximum two-wire interface input frequency. See Figure 19 on page 34.
Table 14.
Two-wire Interface Input AC Timing Specifications
Num
Characteristics
Min
Max
Unit
Notes
1
Start condition hold time
4.0
–
CLKs
(1)(2)
2
Clock low period
(The time before the PC107A will drive SCL low as a
transmitting slave after detecting SCL low as driven by an
external master)
8.0 + (16
×
2
FDR[4:2]
)
×
(5 -
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’11) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
–
CLKs
(1)(2)(4)(5)
3
SCL/SDA rise time (from 0.5V to 2.4V)
–
1
ms
4
Data hold time
0
–
ns
(2)
5
SCL/SDA fall time (from 2.4V to 0.5V)
–
1
mS
6
Clock high period
(Time needed to either receive a data bit or generate a
START or STOP)
5.0
–
CLKs
(1)(2)(5)
7
Data setup time
3.0
–
ns
(3)
8
Start condition setup time (for repeated start condition
only)
4.0
–
CLKs
(1)(2)
9
Stop condition setup time
4.0
–
CLKs
(1)(2)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC107AMZFU100L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
| PC107AMZFU100LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
| PC107AMZFU100LD | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
| PC107AVGHU100L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
| PC107AVGHU100LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
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