參數(shù)資料
型號： P89LPC9107FN,112
廠商： NXP Semiconductors
文件頁數(shù)： 4/39頁
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 1K 14-DIP
標(biāo)準(zhǔn)包裝： 28
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LED，POR，PWM，WDT
輸入/輸出數(shù)： 12
程序存儲器容量： 1KB（1K x 8）
程序存儲器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 14-DIP（0.300"，7.62mm）
包裝： 管件
配用： DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱： 935282288112
P89LPC9107FN
P89LPC9107FN-ND
P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
12 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
Table 5.
P89LPC9103 pin description
Symbol
Pin
Type
Description
P0.1 to P0.5
I/O
Port 0: Port 0 is an I/O port with a user-congurable output type. During reset Port 0
latches are congured in the input-only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port conguration
selected. Each port pin is congured independently. Refer to Section 8.12.1 “Port
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.1/KBI1/
AD10
4
I/O
P0.1 — Port 0 bit 1.
I
KBI1 — Keyboard input 1.
I
AD10 — ADC1 channel 0 analog input.
P0.2/KBI2/
AD11
1
I/O
P0.2 — Port 0 bit 2.
I
KBI2 — Keyboard input 2.
I
AD11 — ADC1 channel 1 analog input.
P0.3/CIN1B/
AD12
10
I/O
P0.3 — Port 0 bit 3.
I
CIN1B — Comparator 1 positive input.
I
AD12 — ADC1 channel 2 analog input.
P0.4/CIN1A/
AD13/DAC1
9
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input.
I
AD13 — ADC1 channel 3 analog input.
O
DAC1 — Digital to analog converter output.
P0.5/CMPREF/
CLKIN
6
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
CLKIN — External clock input.
P1.0 to P1.5
I/O
Port 1: Port 1 is an I/O port with a user-congurable output type. During reset Port 1
latches are congured in the input-only mode with the internal pull-up disabled. The
operation of the congurable Port 1 pins as inputs and outputs depends upon the port
conguration selected. Each of the congurable port pins are programmed
characteristics” for details. P1.5 is input-only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD
5
I/O
P1.0 — Port 1 bit 0.
O
TXD — Serial port transmitter data.
P1.1/RXD
6
I/O
P1.1 — Port 1 bit 1.
I
RXD — Serial port receiver data.
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