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參數資料
| 型號： | P89LPC9107FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 24/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 1K 14-DIP |
| 標準包裝： | 28 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | UART/USART |
| 外圍設備： | 欠壓檢測/復位，LED，POR，PWM，WDT |
| 輸入/輸出數： | 12 |
| 程序存儲器容量： | 1KB（1K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數據轉換器： | A/D 4x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 配用： | DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP 622-1006-ND - SOCKET ADAPTER BOARD 622-1003-ND - KIT FOR LCD DEMO 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名稱： | 935282288112 P89LPC9107FN P89LPC9107FN-ND |
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P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
30 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
8.11.1 External interrupt inputs
The P89LPC9102/9103/9107 has a Keypad Interrupt function. This can be used as an
external interrupt input.
If enabled when the P89LPC9102/9103/9107 is put into Power-down mode or Idle mode,
the interrupt will cause the processor to wake-up and resume operation. Refer to Section
8.14 “Power reduction modes” for details.
Fig 13. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9102)
002aaa976
BOF
EBO
KBIF
EKBI
interrupt
to CPU
wake-up
(if in power-down)
EWDRT
CMF
EC
EA (IE0.7)
RTCF
ERTC
(RTCCON.1)
WDOVF
TF1
ET1
TF0
ET0
ENADCI1
ADCI1
ENBI1
BNDI1
EAD
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| P89LPC912 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM |
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