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參數資料
| 型號： | P89LPC9107FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 30/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 1K 14-DIP |
| 標準包裝： | 28 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | UART/USART |
| 外圍設備： | 欠壓檢測/復位，LED，POR，PWM，WDT |
| 輸入/輸出數： | 12 |
| 程序存儲器容量： | 1KB（1K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數據轉換器： | A/D 4x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 配用： | DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP 622-1006-ND - SOCKET ADAPTER BOARD 622-1003-ND - KIT FOR LCD DEMO 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名稱： | 935282288112 P89LPC9107FN P89LPC9107FN-ND |
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P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
36 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.16.6 Timer overow toggle output (P89LPC9102/9107)
Timers 0 and 1 can be congured to automatically toggle a port output whenever a timer
overow occurs. The same device pins that are used for the T0 and T1 count inputs are
also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the rst
timer overow when this mode is turned on.
8.17 RTC/system timer
The P89LPC9102/9103/9107 has a simple RTC that allows a user to continue running an
accurate timer while the rest of the device is powered-down. The RTC can be a wake-up
or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler
and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be
reloaded again and the RTCF ag will be set. The clock source for this counter is the
CCLK. Only power-on reset will reset the RTC and its associated SFRs to the default
state.
8.18 UART (P89LPC9103/9107)
The P89LPC9103/9107 has an enhanced UART that is compatible with the conventional
80C51 UART except that Timer 2 overow cannot be used as a baud rate source. The
P89LPC9103/9107 does include an independent Baud Rate Generator. The baud rate
can be selected from CCLK (divided by a constant), Timer 1 overow, or the independent
Baud Rate Generator. In addition to the baud rate generation, enhancements over the
standard 80C51 UART include Framing Error detection, automatic address recognition,
selectable double buffering and several interrupt options. The UART can be operated in
four modes: shift register, 8-bit UART, 9-bit UART, and CCLK
32 or
CCLK
16.
8.18.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. Eight bits are
transmitted or received, LSB rst. The baud rate is xed at 1
16 of the CPU clock
frequency.
8.18.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB rst), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1 overow rate or the Baud Rate Generator (described in Section 8.18.5
8.18.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB rst), a programmable 9th data bit, and a stop bit (logic 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.
Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is
received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop
bit is not saved. The baud rate is programmable to either 1
16 or
1
32 of the CPU clock
frequency, as determined by the SMOD1 bit in PCON.
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