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參數(shù)資料
| 型號(hào)： | P89LPC9107FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 32/39頁(yè) |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 1K 14-DIP |
| 標(biāo)準(zhǔn)包裝： | 28 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲(chǔ)器容量： | 1KB（1K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 配用： | DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP 622-1006-ND - SOCKET ADAPTER BOARD 622-1003-ND - KIT FOR LCD DEMO 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名稱： | 935282288112 P89LPC9107FN P89LPC9107FN-ND |
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P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
38 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.18.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.
8.18.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the Tx interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will
be double-buffered together with SBUF data.
8.19 Analog comparators
One analog comparator is provided on the P89LPC9102/9103/9107. Comparator
operation is such that the output is a logic 1 (which may be read in a register) when the
positive input is greater than the negative input (selectable from a pin or an internal
reference voltage). Otherwise the output is a zero. The comparator may be congured to
cause an interrupt when the output value changes.
The connections to the comparator are shown in Figure 16. The comparator functions to
VDD = 2.4 V.
When the comparator is rst enabled, the comparator’s interrupt ag is not guaranteed to
be stable for 10 microseconds. The comparator interrupt should not be enabled during
that time, and the comparator interrupt ag must be cleared before the interrupt is enabled
in order to prevent an immediate interrupt service.
When a comparator is disabled the comparator’s output, COx, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator ag, CMFx. This will
cause an interrupt if the comparator interrupt is enabled. The user should therefore
disable the comparator interrupt prior to disabling the comparator. Additionally, the user
should clear the comparator ag, CMFx, after disabling the comparator.
8.20 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to as
Vref(bg), is 1.23 V ± 3%.
Fig 16. Comparator input and output connections
comparator
CN1
(P0.4) CIN1A
(P0.3) CIN1B
(P0.5) CMPREF
VREF
CO1
002aaa979
change detect
CMF1
interrupt
EC
CP1
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