參數(shù)資料
型號(hào): P89LPC9107FN,112
廠商: NXP Semiconductors
文件頁數(shù): 12/39頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 1K 14-DIP
標(biāo)準(zhǔn)包裝: 28
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 12
程序存儲(chǔ)器容量: 1KB(1K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-DIP(0.300",7.62mm)
包裝: 管件
配用: DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 935282288112
P89LPC9107FN
P89LPC9107FN-ND
P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
2 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
I In-Application Programming (IAP-Lite) and byte erase allows code memory to be used
for non-volatile data storage.
I Serial ash ICP allows simple production coding with commercial EPROM
programmers. Flash security bits prevent reading of sensitive application programs.
I Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
I Low voltage reset (Brownout detect) allows a graceful system shutdown when power
fails. May optionally be congured as an interrupt.
I Idle mode and two different reduced power Power-down modes. Improved wake-up
from Power-down mode (a LOW interrupt input starts execution). Typical Power-down
mode current is less than 1
A (total Power-down mode with voltage comparators
disabled).
I Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available.
I Programmable port output conguration options: quasi-bidirectional, open drain,
push-pull, input-only.
I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
I LED drive capability (20 mA) on all port pins. A maximum limit is specied for the
entire chip.
I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
I Only power and ground connections are required to operate the
P89LPC9102/9103/9107 when internal reset option is selected.
I Four interrupt priority levels.
I Two keypad interrupt inputs.
I Second data pointer.
I External clock input.
I Clock output (P89LPC9102/9107).
I Schmitt trigger port inputs.
I Emulation support.
3.
Product comparison overview
Table 1 highlights the differences between these two devices. For a complete list of device
features, please see Section 2 “Features”.
Table 1.
Product comparison overview
Type number
UART
T0 toggle/PWM
T1 toggle/PWM
CLKOUT
P89LPC9102
-
X
P89LPC9103
X
-
P89LPC9107
XXXX
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