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| 型號： | P89LPC9107FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 31/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 1K 14-DIP |
| 標準包裝： | 28 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | UART/USART |
| 外圍設備： | 欠壓檢測/復位，LED，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 1KB（1K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 配用： | DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP 622-1006-ND - SOCKET ADAPTER BOARD 622-1003-ND - KIT FOR LCD DEMO 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名稱： | 935282288112 P89LPC9107FN P89LPC9107FN-ND |
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P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
37 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.18.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB rst), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overow rate or the Baud Rate Generator (described in
8.18.5 Baud rate generator and selection
The P89LPC9103/9107 enhanced UART has an independent Baud Rate Generator. The
baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0
SFRs which together form a 16-bit baud rate divisor value that works in a similar manner
as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing
functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 15). Note
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses CCLK.
8.18.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7, respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are set up
when SMOD0 is logic 0.
8.18.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device.
8.18.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be
written to SBUF while the rst character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SnBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
Fig 15. Baud rate sources for UART (Modes 1, 3)
baud rate modes 1 and 3
SBRGS = 1
SBRGS = 0
SMOD1 = 0
SMOD1 = 1
timer 1 overflow
(PCLK-based)
baud rate generator
(CCLK-based)
002aaa978
÷2
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