參數(shù)資料
型號: OX12PCI840
廠商: Electronic Theatre Controls, Inc.
英文描述: Integrated Parallel Port and PCI interface
中文描述: 集成的并行端口和PCI接口
文件頁數(shù): 7/32頁
文件大?。?/td> 541K
代理商: OX12PCI840
Data Sheet Revision 1.2
Page 7
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
Pin Numbers
Dir
1
Name
Description
Multi-purpose & External interrupt pins
82, 51
I/O
MIO[1:0]
Multi-purpose I/O pins. Can drive high or low, or assert a PCI
interrupt
EEPROM pins
81
78
80
O
O
IU
EE_CK
EE_CS
EE_DI
EEPROM clock
EEPROM active-high Chip Select
EEPROM data in. When the serial EEPROM is connected,
this pin should be pulled up using 1-10k resistor. When the
EEPROM is not used the internal pull-up is sufficient.
EEPROM data out.
79
O
EE_DO
Miscellaneous pins
77
I
TEST
Test Pin : should be held low at all times
Power and ground
2
8,30,40,56,97
16,45,67,87
V
V
AC VDD
DC VDD
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
Supplies GND to output buffers in switching (AC) state
Ground (0 volts). Supplies GND to core logic, input buffers
and output buffers in steady state
3,7,20,29,35,41,48,55,61,72,92,96
15,44,66,85
G
G
AC GND
DC GND
Table 1: Pin Descriptions
Note 1: Direction key:
I
Input
ID
Input with internal pull-down
O
Output
I/O
Bi-directional
OD
Open drain
NC
No connect
Z
High impedance
Note 2: Power & Ground
There are two GND and two VDD rails internally. One set of rails supply power and ground to output buffers while in switching
state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail).
The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF
radiation from the chip. Further precaution is taken by segmenting the GND and VDD AC rails to isolate the PCI and Local Bus
pins.
P_I
P_O
P_I/O
P_OD
G
V
PCI input
PCI output
PCI bi-directional
PCI open drain
Ground
5.0V power
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