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參數(shù)資料
| 型號： | OX12PCI840 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Parallel Port and PCI interface |
| 中文描述： | 集成的并行端口和PCI接口 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大?。?/td> | 541K |
| 代理商： | OX12PCI840 |
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4.4
Data Sheet Revision 1.2
Page 12
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
Accessing Local configuration registers
The local configuration registers are a set of device specific registers which can always be accessed. They are mapped to the
I/O and memory addresses set up in BAR2 and BAR3, with the offsets defined for each register. I/O or memory accesses can be
byte, word or dword accessed, however on little-endian systems such as Intel 80x86 the byte order will be reversed.
4.4.1
Local Configuration and Control register ‘LCC’ (Offset 0x00)
This register defines control of ancillary functions such as Power Management, endian selection and the serial EEPROM. The
individual bits are described below.
Bits
Description
2:0
Reserved
4:3
Endian Byte-Lane Select for memory access to parallel port
00 = Select Data[7:0] 10 = Select Data[23:16]
01 = Select Data[15:8] 11 = Select Data[31:24]
Memory access to OX12PCI840 is always DWORD aligned. When
accessing the parallel port, this option selects the active byte lane. As
both PCI and PC architectures are little endian, the default value will be
used by systems, however, some non-PC architectures may need to
select the byte lane.
7:5
Power-down filter time. These bits define a value of an internal filter time
for power-down interrupt request in power management circuitry in
Function0. Once Function0 is ready to go into power down mode,
OX12PCI840 will wait for the specified filter time and if Function0 is still
in power-down request mode, it can assert a PCI interrupt (see section
4.6).
000 = power-down request disabled
001 = 4 seconds
011 = 518 seconds
1XX = Immediate
10:8
Reserved: Power management test bits. The device driver must write
zero to these bits
22:11
Reserved.
23
Parallel port Input (glitch) filters. Enabled when ‘1’
24
EEPROM Clock. For PCI read or write to the EEPROM , toggle this bit to
generate an EEPROM clock (EE_CK pin).
25
EEPROM Chip Select. When 1 the EEPROM chip-select pin EE_CS is
activated (high). When 0 EE_CS is de-active (low).
26
EEPROM Data Out. For writes to the EEPROM, this output bit is the
input-data of the EEPROM. This bit is output on EE_DO and clocked into
the EEPROM by EE_CK.
27
EEPROM Data In. For reads from the EEPROM, this input bit is the
output-data of the EEPROM connected to EE_DI pin.
28
EEPROM Valid. A 1 indicates that a valid EEPROM program is present
29
Reload configuration from EEPROM. Writing a 1 to this bit re-loads the
configuration from EEPROM. This bit is selfclearing after EEPROM read
30
Reserved
31
Reserved
Read/Write
EEPROM
W
Reset
000
00
PCI
RW
W
RW
000
010 = 129 seconds
-
R
000
-
W
-
R
RW
RW
0000h
0
0
-
RW
0
-
RW
0
-
R
X
-
-
R
RW
X
0
-
-
R
R
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
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| OX12PCI840-PQAG | 功能描述:外圍驅(qū)動器與原件 - PCI PCI bridge to parallel port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| OX1440 | 制造商:RALTRON 制造商全稱:RALTRON 功能描述:OCXO |
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