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參數(shù)資料
| 型號： | OX12PCI840 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Parallel Port and PCI interface |
| 中文描述： | 集成的并行端口和PCI接口 |
| 文件頁數(shù)： | 13/32頁 |
| 文件大小： | 541K |
| 代理商： | OX12PCI840 |
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4.4.2
This register configures the operation of the multi-purpose I/O pins ‘MIO[1:0] as follows.
Bits
Description
1:0
MIO0 Configuration Register
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
3:2
MIO1 Configuration Register
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
4
MIO0_PME Enable. A value of ‘1’ enables MIO0 pin to set the
PME_Status in PMCSR register, and hence assert the PME# pin if
enabled. A value of ‘0’ disables MIO0 from setting the PME_Status bit.
5
MIO1_PME Enable. A value of ‘1’ enables MIO1 pin to set the
PME_Status in PMCSR register, and hence assert the PME# pin if
enabled. A value of ‘0’ disables MIO1 from setting the PME_Status bit.
6
MIO0 Power Down Request: A ‘1’ enables MIO0 to control the power
down request filter.
7
MIO1 Power Down Request: A ‘1’ enables MIO1 to control the power
down request filter.
31:8
Reserved
4.4.3
Local Bus Timing Parameter register 1 ‘LT1’ (Offset 0x08):
The Local Bus Timing Parameter registers (LT1 and LT2) define the operation and timing parameters used by the internal local
bus (that connects to the parallel port).
It is envisaged that these should not need to be changed by the user
. The timing
parameters are programmed in 4-bit registers to define the assertion/de-assertion of the Local Bus control signals. The values
programmed in these registers defines the number of PCI clock cycles after a Reference Cycle when the events occur, where
the reference Cycle is defined as two clock cycles after the master asserts the IRDY# signal. The timings refer to I/O or Memory
mapped accesses.
Bits
Description
3:0
Read Cycle start
7:4
Read Cycle end
11:8
Write Cycle start
15:12
Write Cycle end
19:16
Read Assertion
23:20
Read De-assertion
27:24
Write Assertion
31:28
Write De-assertion
Note 1:
Only values in the range of 0h to Ah (0 -10 decimal) are valid. Other values are reserved. See notes in the following page.
Data Sheet Revision 1.2
Page 13
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
Multi-purpose I/O Configuration register ‘MIC’ (Offset 0x04)
Read/Write
EEPROM
W
Reset
00
PCI
RW
W
RW
00
W
RW
0
W
RW
0
W
RW
0
W
RW
0
-
R
00
Read/Write
EEPROM
W
W
W
W
W
W
W
W
Reset
0h
2h
0h
2h
1h
2h
1h
2h
PCI
RW
RW
RW
RW
RW
RW
RW
RW
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OX12PCI840-PQAG | 功能描述:外圍驅(qū)動器與原件 - PCI PCI bridge to parallel port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| OX1340 | 制造商:RALTRON 制造商全稱:RALTRON 功能描述:OCXO |
| OX1341 | 制造商:RALTRON 制造商全稱:RALTRON 功能描述:OCXO |
| OX1440 | 制造商:RALTRON 制造商全稱:RALTRON 功能描述:OCXO |
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