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參數(shù)資料
| 型號(hào)： | OX12PCI840 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Parallel Port and PCI interface |
| 中文描述： | 集成的并行端口和PCI接口 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 541K |
| 代理商： | OX12PCI840 |
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4.4.5
Data Sheet Revision 1.2
Page 15
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
Global Interrupt Status and Control Register ‘GIS’ (Offset 0x10)
Bits
1:0
2
Description
Reserved
MIO0 This bit reflects the state of the internal MIO[0]. The internal MIO[0]
reflects the non-inverted or inverted state of MIO0 pin.
MIO1 This bit reflects the state of the internal MIO[0]. The internal MIO[0]
reflects the non-inverted or inverted state of MIO0 pin.
Reserved
MIO0 INTA enable
When set (1) allows MIO0 to assert a PCI interrupt on the INTA line. State of
MIO0 that causes an interrupt is dependant upon the polarity set by MIC(1:0)
MIO1 INTA enable
When set (1) allows MIO1 to assert a PCI interrupt on the INTA line. State of
MIO1 that causes an interrupt is dependant upon the polarity set by MIC(3:2)
Power-down Interrupt This is a sticky bit. When set, it indicates a power-down
request issued and would normally have asserted a PCI interrupt if bit 21 was
set (see section 7.9). Reading this bit clears it.
Power-down interrupt enable. When ‘1’ a power down request is allowed to
generate an interrupt.
Parallel port interrupt status
Parallel port interrupt enable
Read/Write
EEPROM
-
-
-
-
W
Reset
PCI
R
R
0x0h
X
3
R
X
17-4
18
R
RW
0
0
19
W
RW
0
20
-
R
X
21
W
RW
0
22
23
-
W
R
RW
0
1
31:24
Reserved
-
R
000h
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OX12PCI840-PQAG | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI bridge to parallel port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| OX1340 | 制造商:RALTRON 制造商全稱:RALTRON 功能描述:OCXO |
| OX1341 | 制造商:RALTRON 制造商全稱:RALTRON 功能描述:OCXO |
| OX1440 | 制造商:RALTRON 制造商全稱:RALTRON 功能描述:OCXO |
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