參數(shù)資料
型號(hào): OX12PCI840
廠商: Electronic Theatre Controls, Inc.
英文描述: Integrated Parallel Port and PCI interface
中文描述: 集成的并行端口和PCI接口
文件頁(yè)數(shù): 10/32頁(yè)
文件大小: 541K
代理商: OX12PCI840
4.2.1
Data Sheet Revision 1.2
Page 10
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
PCI Configuration Space Register map
Configuration Register Description
16
Offset
Address
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
31
15
0
Device ID
Status
Vendor ID
Command
Class Code
Header Type
Revision ID
Reserved
BIST
1
Reserved
Base Address Register 0 (BAR0) - Function in I/O space
Base Address Register 1 (BAR 1) - Function in I/O space
Base Address Register 2 (BAR 2) – Local Configuration Registers in IO space
Base Address Register 3 (BAR3) – Local Configuration Registers in Memory space
Base Address Register 4 (BAR4) – Function in Memory Space
Reserved
Reserved
Subsystem ID
Reserved
Reserved
Reserved
Reserved
Reserved
Power Management Capabilities (PMC)
Reserved
Reserved
Subsystem Vendor ID
Cap_Ptr
InterruptPin
Next Ptr
PMC Control/Status Register (PMCSR)
Interrupt Line
Cap_ID
Table 2: PCI Configuration space
Program read/write
EEPROM
W
W
-
W(bit 4)
-
W
-
-
-
-
-
-
W
Register name
Reset value
PCI
R
R
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R
Vendor ID
Device ID
Command
Status
Revision ID
Class code
Header type
BAR 0
BAR 1
BAR 2
BAR 3
BAR 4
Subsystem VID
0x1415
0x8403
0x0000
0x0290
0x00
0x070103
0x00
0x00000001
0x00000001
0x00000001
0x00000000
Reserved
0x1415
Subsystem ID
Cap ptr.
Interrupt line
Interrupt pin
Cap ID
Next ptr.
PM capabilities
PMC control/ status register
0x0001
0x40
0x00
0x01
0x01
0x00
0x6C01
0x0000
W
-
-
W
-
-
W
-
R
R
R/W
R
R
R
R
R/W
Table 3: PCI configuration space default values
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