參數(shù)資料
型號(hào)： ORT8850L
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁(yè)數(shù)： 65/112頁(yè)
文件大小： 2417K
代理商： ORT8850L
Agere Systems Inc.
65
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Pin Information
(continued)
Table 29. FPGA Common-Function Pin Description
(continued)
Symbol
I/O
Description
A[0:17]
MPI_BURST
MPI_BDIP
MPI_TSZ[1:0]
I
During MPI mode, the A[0:17] are used as the address bus driven by the
PowerPC
bus
master, utilizing the least significant bits of the
PowerPC
32-bit address.
During master parallel configuration mode, A[0:17] address the configuration EPROM. In
MPI mode, many of the A[n] pins have alternate uses as described below. See the special
function blocks section for more MPI information. During configuration, if not in master
parallel or an MPI configuration mode, these pins are 3-stated with a pull-up enabled.
It is driven low to indicate a burst transfer is in progress. Driven high indicates that the
current transfer is not a burst.
It is driven by the
PowerPC
processor assertion of this pin indicates that the second beat
in front of the current one is requested by the master. Negated before the burst transfer
ends to abort the burst data phase.
MPI_TSZ[1:0] signals and are driven by the bus master to indicate the data transfer size
for the transaction. Set 10 for byte, 01 for half-word, and 00 for word.
If not used for MPI, these pins are user-programmable I/O pins.*
In
PowerPC
mode MPI operation, this is driven low indicating the MPI received the data
on the write cycle or returned data on a read cycle.
This is the
PowerPC
synchronous, positive-edge bus clock used for the MPI interface. It
can be a source of the clock for the embedded system bus. If MPI is used, this can be the
AMBA
bus clock.
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on
the internal system bus for the current transaction.
This pin requests that the MPC860 relinquish the bus and retry the cycle.
I/O Selectable data bus width from 8-, 16-, 32-bit. Driven by the bus master in a write transac-
tion. Driven by MPI in a read transaction.
I
D[0:7] receive configuration data during master parallel, peripheral, and slave parallel
configuration modes and each pin has a pull-up enabled. During serial configuration
modes, D0 is the DIN input.
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
After configuration, the pins are user-programmable I/O pins.*
I/O Selectable parity bus width from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for
D[16:23], and DP[3] for D[24:32].
After configuration, this pin is a user-programmable I/O pin.*
I
During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input.
During configuration, a pull-up is enabled.
I/O After configuration, this pin is a user-programmable I/O pin.*
O
During configuration, DOUT is the serial data output that can drive the DIN of daisy-
chained slave devices. Data out on DOUT changes on the rising edge of CCLK.
I/O After configuration, DOUT is a user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the acti-
vation of all user I/Os) is controlled by a second set of options.
O
MPI_ACK
O
MPI_CLK
I
MPI_TEA
O
MPI_RTRY
D[0:31]
O
DP[3:0]
DIN
DOUT
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ORT8850L-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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