參數(shù)資料
型號(hào)： ORT8850L
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁(yè)數(shù)： 35/112頁(yè)
文件大?。?/td> 2417K
代理商： ORT8850L
Agere Systems Inc.
35
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
RapidIO
Interface to Pi-Sched
(continued)
0676
Figure 14.
RapidIO
Receive Cell Interface
Octets and Start of Cell
Cells will be transmitted on the high-speed LVDS inputs as octets. The first octet o0 (consisting of
d0_0, d1_0 . . . d7_0) will be present on bits 31:24 on the low-speed 32-bit FPGA bus. Similarly, octet o1 (consist-
ing of d0_1, 1_1 . . . d7_1) will be present on bits 23:16 on the 32-bit bus. Thus, octets will always be transmitted
from first octet to last. The minimum number of octets present on the high-speed ports should always be divisible
by 4, evenly representing the relationship with the 32-bit core of the ASIC interface. The start-of-cell signal is
always aligned with the first octet of each cell. Once the first octet of a cell is received, subsequent octets are part
of an uninterrupted data stream until the entire cell has been received. The number of octets in a cell is determined
by the register bits OCELLSIZE. The
RapidIO
can support varying minimum cell sizes from four octets up to 124 in
increments of 4. The
RapidIO
is programmed with the cell size by writing to the OCELLSIZE register via the micro-
processor interface. If the transmitted cell size is less than the programmed cell size, a violation occurs and the
IRXSOCVIOL flag is active. This flag can be ignored if a given minimum cell size is not needed.
D
CLK
Q
RXCLK
RXSOC
D
CK
Q
ZRXD_7
ZRXD_23
ZRXD_31
ZRXD_15
WRXCLK
(133 MHz)
TO
FPGA
133 MHz CLOCK DOMAIN
266 MHz CLOCK DOMAIN
INPUT
DATA
CAPTURE
REPEATED 7 TIMES (ONE FOR EACH OF RXD[1:7])
D
Q
ZRXSOC
D
Q
D
Q
D
Q
RXD[7]
RXD[0]
D
CLK
Q
SHIFT REGISTERS
D
CK
Q
D
CK
Q
D
CK
Q
D
CK
Q
D
CK
Q
D
CK
Q
D
CK
Q
D
CK
Q
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ORT8850L-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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