參數(shù)資料
型號(hào)： ORT8850L
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁(yè)數(shù)： 17/112頁(yè)
文件大小： 2417K
代理商： ORT8850L
Agere Systems Inc.
17
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Generic Backplane Transceiver
Application
Synchronous Transfer Mode (STM)
The combination of ORT8850 and soft IP cores pro-
vides a generic data moving solution for non-SONET
applications. There is no requirement for SONET
knowledge to the users. All that is needed is to supply
the pseudo-SONET framer with data, clock, and a
8 kHz frame pulse. The provision registers may also
need to be set up, and this can be done through either
the FPGA MPI, or in a state machine in the FPGA sec-
tion (VHDL code available from Agere).
The 8 kHz frame pulse must be supplied to the
SYS_FP signal. For generic applications, the frame
pulse can be created in FPGA logic from the
77.76 MHz SYS_CLK using a simple resettable
counter (the frame pulse should only be high for one
cycle of the SYS_CLK). A VHDL core that automati-
cally provides the 8 kHz frame pulse is available from
Agere. Byte-wide data is then sent to each of the trans-
mit channels as follows: the first 36 bytes transferred
will be invalid data (replaced by overhead), where the
first byte is sent on the rising edge of SYS_CLK when
SYS_FP is high. The next 1044 byte positions can be
filled with valid data. This will repeat a total of nine
times (36 invalid bytes followed by
1044 valid bytes) at which time the next 8 kHz frame
pulse will be found. Thus, 87 out of 90 (96.7%) of the
data bytes sent are valid user data. The ORT8850 also
supports a transparent mode where only the first
24 bytes are invalid data (A1/A2 frame bytes) followed
by 9,684 bytes of valid user data.
On the receive side, an 8 kHz pulse must again be sup-
plied to LINE_FP. In this case, however, only the signal
DOUT<channel>_SPE (where the eight channels are
labeled AA, AB, AC, AD, BA, BB, BC, and BD) must be
monitored for each channel, where a high value on this
signal means valid data. Again, 87 out 90 bytes
received (96.7%) will be valid data. Transparent mode
is also supported for receive data.
8B/10B Mode
The ORT8850 facilitates high-speed serial transfer of
data in a variety of applications including Gigabit
Ethernet, fibre channel, serial backplanes, and
proprietary links. In place of the STM interface, the
ORT8850 also provides 8B/10B coding/decoding for
each channel. The 8B/10B transmission code includes
serial encoding/decoding rules, special characters, and
error detection. In 8B/10B mode, LSB is received first
and transmitted first. The 10-bit encoded transmission
characters labeled as a, b, c, d, e, i, f, g, h, and j are
transmitted with bit a first and bit j last, where bit a is
the LSB and bit j is the MSB.
Transmitter Description
The data input to the transmitter of each channel is an
8-bit word and a K-control input. The K input is used to
identify data or a special character. For each channel,
the input data byte is clocked into a FIFO. When K-con-
trol is 1, the data on the parallel input is mapped into its
corresponding control character. The transmit FIFOs
must be initialized upon the deassertion of the RST_N
signal.
Receiver Description
Clock recovery is performed by the HSI on the input
data stream for each channel of the ORT8850. The
recovered data is then aligned to the 10-bit word
boundary. Word alignment is accomplished by detect-
ing and aligning to the 8B/10B comma sequence. The
HSI will detect and align to either polarity of the comma
sequence. The 10-bit word aligned data is then
decoded and the 8-bit output is passed to the align-
ment FIFOs. Each receive channel provides a FIFO in
order to adjust for the skew between the channels and
ensure that the first valid data following the comma
character is transmitted simultaneously from all the
channels that are programmed to be aligned.
In the RESET state, each channel is actively searching
for the occurence of a comma character. Once the
channel is powered up, the comma detect pulse will be
found on the doutxx-fp per channel in the FPGA.
Receive Channel Sync Block
In order to account for skews between the channels, it
is necessary to align multiple channels on the comma
character boundary. The sync algorithm assumes that
either all eight channels, two groups of four channels,
or four groups of two channels will be aligned. The
ORT8850 powers up in the RESET state in which no
channel alignment is done.
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ORT8850L-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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