參數(shù)資料
型號： ORSO82G5-3F680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 96/153頁
文件大小： 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
47
ORSO42G5 Conguration
At startup, the legacy SERDES channel logic must be powered down and removed from any multi-channel align-
ment groups:
Setting bit 1 to one in registers at locations 30002, 30012, 30102 and 30112 powers down the legacy logic. (Note
that the reset value for these bits is 0.)
Setting bit 1 to zero (reset condition) in the register at locations 30802, 30812, 30902 and 30912 removes the
legacy logic from any alignment group.
Register settings for SONET multi-channel alignment are shown in Table 7.
Table 7. Multichannel Alignment Modes – ORSO42G5
To align two channels in SERDES A:
FMPU_SYNMODE_AC = 01 (Register Location 30822)
FMPU_SYNMODE_AD = 01 (Register Location 30832)
To align two channels in SERDES B:
FMPU_SYNMODE_BC = 01 (Register Location 30922)
FMPU_SYNMODE_BD = 01 (Register Location 30932)
To align all four channels:
FMPU_SYNMODE_AC = 11 (Register Location 30822)
FMPU_SYNMODE_AD = 11 (Register Location 30832)
FMPU_SYNMODE_BC = 11 (Register Location 30922)
FMPU_SYNMODE_BD = 11 (Register Location 30932)
To enable/disable multi-channel alignment of individual channels within a multi-channel alignment group:
FMPU_STR_EN_xx = 1 enabled
FMPU_STR_EN_xx = 0 disabled
where xx = [AC,AD,BC,BD]
To resynchronize a multichannel alignment group set the following bits to one, and then set to zero:
FMPU_RESYNC4 for four channels, AC, AD, BC and BD. (Register Location 30A04, bit 7)
FMPU_RESYNCA2 for dual channels, AC and AD. (Register Location 30A04, bit 2)
FMPU_RESYNCB2 for dual channels, BC and BD. (Register Location 30A04, bit 5)
To resynchronize an independent channel (resetting the write and the read pointer of the FIFO) set the following
bits to one, and then set to zero.
FMPU_RESYNC1_xx (Register Locations 30824, 20834, 30924 and 30934, bit 7) where xx is one of AC, AD, BC
or BD.
Register Bits
FMPU_SYNMODE_xx[2:3]
Mode
00
No multichannel alignment
01
Twin channel alignment
11
Four channel alignment
Note: xx = [AC,AD,BC,BD]
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