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| 型號(hào)： | ORSO82G5-3F680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 86/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
38
Figure 23. Receive Clocking Diagram for SONET Mode Quad-Channel Alignment in Block A – ORSO42G5
Multi-channel Alignment in SONET Mode (ORSO82G5)
The alignment FIFO allows the transfer of all data to a common clock. The FIFO sync block allows the system to be
congured to allow the frame alignment of multiple slightly varying data streams. This optional alignment ensures
that matching SERDES streams will arrive at the FPGA end in perfect data sync. It is important to note that for all
aligned channels in a group, the SERDES transmitters on the other side of the high-speed link must all be transmit-
ting data at exactly the same frequency (0 ppm difference), i.e., using a common clock source.
The ORSO82G5 has a total of eight channels (four per SERDES block). The incoming data of these channels can
be synchronized in several ways, or they can be independent of one other. Two channels within a SERDES can be
aligned together; channel A and B and/or channel C and D can form a pair as shown in Figure 24. Alternately, all
four channels in a SERDES block can be aligned together to form a communication channel with a bandwidth of 10
Gbps as shown in Figure 25.
Finally, the alignment can be extended across the SERDES blocks to align all eight channels in the ORSO82G5 as
shown in Figure 26. Individual channels within an alignment group can be disabled (i.e., powered-down) without
disrupting other channels. Note that the SERDES channel that is powered down can not be the source of the RSY-
SCLKxx that is clocking the read side of the alignment FIFO. When a disabled channel becomes active as part of
an alignment group, the group may need to be re-aligned. Then the whole group needs to be resynched. This
would only need to occur if the transmitting frame pulse for the new link is different from the rest of the group.
FPGA
RCK78A
RWCKAD
RWCKBC
RWCKBD
RWCKAC
SPE
Generator
SPE
Generator
SPE
Generator
SPE
Generator
Alignment
FIFO
Alignment
FIFO
Alignment
FIFO
Alignment
FIFO
Framer,
Descrambler
Framer,
Descrambler
Framer,
Descrambler
Framer,
Descrambler
Logic Common to Block
Common
155.52 MHz
SERDES
DEMUX
RSYSCLKA2
Channel AC
Channel AD
HDIN[P:N]_AC
2.488 Gbits/s
SERDES
HDIN[P:N]_AD
2.488 Gbits/s
DEMUX
SERDES
DEMUX
RSYSCLKB2
Channel BC
Channel BD
HDIN[P:N]_BC
2.488 Gbits/s
SERDES
HDIN[P:N]_BD
2.488 Gbits/s
DEMUX
REFCLKA[P,N]
REFCLKB[P,N]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO82G5-3FN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 2.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-G2-PAC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORSO82G5-FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSPI4 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Dual SPI4 Interface and High-Speed SERDES FPSC |
| ORSPI4-1F1156C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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