參數(shù)資料
型號： ORSO82G5-3F680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 10/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
107
30A0D
[0]
RSVD
00
Reserved
—
[1]
SYNC4_B_OVFL
SYNC8_OOS = 1 indicates that the alignment
FIFO(s) in the links in block B are near overow
(i.e., at the time of writing into address 0, the
read address was less than RX_FIFO_MIN)
SONET
[2]
SYNC2_B2_OVFL
SYNC2_B2_OVFL = 1 indicates that the align-
ment FIFO(s) in the links BC and BD are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[3]
SYNC2_B1_OVFL
SYNC2_B1_OVFL = 1 indicates that the align-
ment FIFO(s) in the links BA and BB are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[4]
SYNC4_A_OVFL
SYNC4_A_OVFL = 1 indicates that the align-
ment FIFO(s) in the links in block A are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[5]
SYNC2_A2_OVFL
SYNC2_A2_OVFL = 1 indicates that the align-
ment FIFO(s) in the links AC and AD are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[6]
SYNC2_A1_OVFL
SYNC2_A1_OVFL = 1 indicates that the align-
ment FIFO(s) in the links AA and AB are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[7]
SYNC8_OVFL
SYNC8_OVFL = 1 Indicates that the alignment
FIFO(s) in eight-links are near overow (At the
time of writing into address 0, the read address
was less than RX_FIFO_MIN)
SONET
30A0E
[0:2]
RSVD
00
Reserved
—
[3]
BDL_ALIGN_ERR_B2
Alignment Error, BDL_ALIGN_ERR = 1 indi-
cates that an alignment error has occurred in
the link group pairs BC and BD
Cell
[4]
BDL_ALIGN_ERR_B1
Alignment Error, BDL_ALIGN_ERR = 1 indi-
cates that an alignment error has occurred in
the link group pairs BA and BB
Cell
[5]
BDL_ALIGN_ERR_A2
Alignment Error, BDL_ALIGN_ERR = 1 indi-
cates that an alignment error has occurred in
the link group pairs AC and AD
Cell
[6]
BDL_ALIGN_ERR_A1
Alignment Error, BDL_ALIGN_ERR = 1 indi-
cates that an alignment error has occurred in
the link group pairs AA and AB
Cell
[7]
BDL_ALIGN_ERR_ALL8
BDL_ALIGN_ERR_ALL8 = 1 -indicates that an
alignment error has occurred in cell group of all
eight-links
Cell
Table 36. Common Control Register Descriptions – ORSO82G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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參數(shù)描述
ORSO82G5-3FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 2.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-G2-PAC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORSO82G5-FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSPI4 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-1F1156C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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