參數(shù)資料
型號： ORSO82G5-3F680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 124/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
72
Toggle GSWRST_[A:B] to clear the RX FIFOs
– 30005
20
– 30105
20
– 30005
00
– 30105
00
Clear the Rejoin register bits and set Auto_Bundle
– 30A03
49
5. Eight-Link Cell Mode Initialization – ORSO82G5
This sample initialization uses 8-link cell mode. Auto_Bundle and Auto_Remove are both used for these links. The
GSWRST_[A:B] Rejoin method is used.
Set SERDES PLL to Lock to Data signal and Auto_TOH mode (per channel, all channels)
– 30804, etc. 82
Set Auto_Remove, and Rejoin
– 30A03
1B
Set 8-link cell mode
– 30A05
01
Toggle SOFT_RESET
– 30A06
01
– 30A06
00
Set the TX_CFG_DONE bit to indicate the transmitter is completely congured
– 30A07
01
Toggle GSWRST_[A:B] to clear the Rx FIFOs
– 30005
20
– 30105
20
– 30005
00
– 30105
00
Once all of the RX_LINK_GOODs are high, Clear the Rejoin register bits and set Auto_Bundle
– 30A03
49
Reset Conditions
The SERDES block can be reset in one of three different ways: on power up, using the hardware reset
(PASB_RESETN) or by setting bits in the control registers. The power up reset process begins when the power
supply voltage ramps up to approximately 80% of the nominal value of 1.5V. Following this event, the device will be
ready for normal operation after 3 ms.
A hardware reset is initiated by making the PASB_RESETN low for at least two microprocessor clock cycles. The
device will be ready for operation 3 ms after the low to high transition of the PASB_RESETN. This reset function
affects all SERDES blocks and resets all core control, status and data path registers and counters.
Using the software reset option, each channel can be individually reset by setting SWRST bit to a logic 1 in the
SERDES channel conguration register. The device will be ready 3 ms after the SWRST bit is deasserted. Simi-
larly, all four channels per block SERDES can be reset by setting the global reset bit GSWRST. The device will be
ready for normal operation 3 ms after the GSWRST bit is deasserted. Note that the software reset options resets
only the SERDES internal registers and counters on a per channel or per block basis. The core non-SERES regis-
ters and logic blocks are not affected. It should also be noted that the embedded core registers and logic blocks
cannot be accessed until after FPGA conguration is complete.
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ORSO82G5-3FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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