參數(shù)資料
型號： OR3TP12-6BA352
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 83/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA352
Lucent Technologies Inc.
Lucent Technologies Inc.
83
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed Description
(continued)
Table 25. Configuration Space Assignment
1. These values are intended to be custom assigned, per the intended application, by assigning constants via the FPGA configuration manager.
2. These bits exhibit special behavior per the PCI Specification:
— Reads behave normally.
— Writing a one clears the bit to 0.
— Writing a 0 has no effect on the bit.
3. Bytes 10—27 hex contain the base address registers (BARs).
— Any legal combination of memory and I/O BARs is permitted, as long as 64-bit BARs are naturally aligned, that is, they occupy bytes
10—17, 18—1F, or 20—27 hex.
— Memory BARs may be marked as prefetchable/nonprefetchable by setting/resetting bit 3; however, the PCI bus core’s behavior is not
affected by this setting. In particular, the Target read operation may discard unused FIFO read-ahead data even though the data space is
marked as nonprefetchable (this is not a violation since the nonprefetchable bit only says that data can’t be discarded once it has been
sent over the PCI bus; nevertheless, caution must be exercised when this bit is reset).
4. These signals are tied to the FPGA signal of the same name and are not initialized.
5. These bits exhibit special behavior per the CompactPCIHot Swap Specification:
— Reads behave normally.
— Writing a one clears the bit to 0.
— Writing a 0 has no effect on the bit.
6. This 32-bit register is used during manufacturing test. Writes are not allowed; reads are allowed and cause no side effects, but the value
returned is undefined.
Bytes
Width
Bit
Description
Read/Write
Initial Value after FPGA
Configuration
11C1h (Lucent)
5400h (OR3TP12)
00—01
02—03
04—05
16
16
16
—
—
Vendor ID
Device ID
Command:
Enable I/O Space
Enable Memory Space
Enable Bus Master
Enable Special Cycle
Enable Mem Wr & Inv
Enable VGA Palette Snoop
Enable Par Err Response
Enable Stepping
Enable
serrn
Enable Fast Back-to-Back
Reserved
Status:
Reserved
Capabilities List
66 MHz Capable
UDF Supported
Fast Back-to-Back
Master Data Parity Error
devseln
Timing
Target Abort Signaled
Target Abort Received
Master Abort Received
System Error Signaled
Parity Error Detected
Read Only
Read Only
0
1
2
3
4
5
6
7
8
9
15—10
Read/Write
Read/Write
Read/Write
Read Only
Read Only
Read Only
Read/Write
Read Only
Read/Write
Read/Write
Read Only
0
0
Note 1
0
0
0
0
0
0
0
zeros
06—07
16
3—0
4
5
6
7
8
10—9
11
12
13
14
15
Read Only
Read Only
Read Only
Read Only
Read Only
Note 2
Read Only
Note 2
Note 2
Note 2
Note 2
Note 2
zeros
1
1
0
1
0
01b (medium)
0
0
0
0
0
相關(guān)PDF資料
PDF描述
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
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參數(shù)描述
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OR3TP12-6BA352I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
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OR3TP12-6PS240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
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