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| 型號(hào)： | OR3TP12-6BA352 |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE |
| 中文描述： | 用戶(hù)可編程ASIC的特殊功能 |
| 文件頁(yè)數(shù)： | 102/128頁(yè) |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12-6BA352 |
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
102
L Lucent Technologies Inc.
Symbol
I/O
Description
Dedicated Pins
V
DD
GND
RESET
—
—
I
Positive power supply.
Ground supply.
During configuration, RESET forces the restart of configuration and a pull-up is
enabled. After configuration, RESET can be used as an FPGA logic direct input,
which causes all PLC latches/FFs to be asynchronously set/reset.
In the Master and asynchronous peripheral modes, CCLK is an output which strobes
configuration data in. In the slave or synchronous peripheral mode, CCLK
is input synchronous with the data on DIN or D[7:0]. In microprocessor and PCI
modes, CCLK is used internally and output for daisy-chain operation.
As an input, a low level on DONE delays FPGA start-up after configuration.*
As an active-high, open-drain output, a high level on this signal indicates that config-
uration is complete. DONE is also used in the embedded PCI core start-up
sequence. DONE has an optional pull-up resistor.
PRGM is an active-low input that forces the restart of configuration and resets the
boundary-scan circuitry. This pin always has an active pull-up.
This pin must be held high during device initialization until the INIT pin goes high.
This pin always has an active pull-up.
During configuration, RD_CFG is an active-low input that activates the TS_ALL
function and 3-states all of the I/O.
After configuration, RD_CFG can be selected (via a bit stream option) to activate the
TS_ALL function as described above, or, if readback is enabled via a bit stream
option, a high-to-low transition on RD_CFG will initiate readback of the configuration
data, including PFU output states, starting with frame address 0.
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides con-
figuration data out. If used in boundary scan, TDO is test data out.
CCLK
I
DONE
I
O
PRGM
I
RD_CFG
I
RD_DATA/TDO
O
Special-Purpose Pins
M0, M1, M2
I
I/O
I
During powerup and initialization, M0—M2 are used to select the configuration
mode with their values latched on the rising edge of INIT; see Table 28 for the con-
figuration modes. During configuration, a pull-up is enabled.
After configuration, M2 can be a user-programmable I/O.*
During powerup and initialization, M3 is used to select the speed of the internal
oscillator during configuration with their values latched on the rising edge of INIT.
When M3 is low, the oscillator frequency is 10 MHz. When M3 is high, the oscillator
is 1.25 MHz. During configuration, a pull-up is enabled.
After configuration, M2 can be a user-programmable I/O pin.*
M3
I/O
* The ORCASeries 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
Pin Information
This section describes the pins and signals that perform FPGA-related functions. Any pins not described in Table 5
or here in Table 41 are user-programmable I/Os. During configuration, the user-programmable I/Os are 3-stated
and pulled-up with an internal resistor. If any FPGA function pin is not used (or not bonded to package pin), it is
also 3-stated and pulled-up after configuration.
Table 41. FPGA Common-Function Pin Descriptions
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3TP12-6BA352I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
| OR3TP12-6PS240I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| OR3TP12 | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| OR62 | OR62 is a 6-input OR gate with 2x drive strength |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA352I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BAN256-DB | 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR3TP12-6PS240 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP12-6PS240I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:User Programmable Special Function ASIC |
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