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| 型號： | OR3TP12-6BA352 |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 24/128頁 |
| 文件大小： | 2450K |
| 代理商： | OR3TP12-6BA352 |
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
24
L Lucent Technologies Inc.
Symbol
I/O
Description
Clock
Domain
Master Read Data FIFO Signals
(continued)
mr_stopburstn
O
Stop Burst Reads.
This active-low signal is used by the FPGA application to
terminate Master reads before the read burst length is reached. The Master
must be transferring data on the PCI bus for this signal to be effective, and it is
recommended to hold this signal until
ma_fulln
is deasserted. Once asserted,
this signal needs to remain asserted for a minimum of two
pciclk
cycles.
pciclk
Target General
tfifoclrn
O
Target FIFO Clear
. This active-low signal is asynchronously asserted by the
FPGA application to clear the Target address, read, and write data FIFOs,
along with
tstatecntr
. This signal does not reset the Target controller’s PCI
state machine, and it is not recommended to be used to terminate the current
PCI transaction.
Target Logic Ready.
This active-high signal indicates that the Target FIFO
interface to the FPGA application is ready. This signal will be inactive during
PCI bus resets, Target FIFO clears, and up to 16 clocks after device configura-
tion. This signal can be ignored when transferring data from the Target write
data FIFO, if
pci_rstn
is inactive.
Target State Counter.
Indicates the current state of the Target FIFO interface.
Details of the Target FIFO interface can be found in the PCI Bus Core Target
Controller Detailed Description section of this data sheet.
Discard Timer Expired.
This active-low signal indicates that the discard timer
has expired and the Target controller has deleted the current transaction which
was stored as a delayed transaction. The FPGA application should discontinue
processing of the current Target transaction. The discard timer is a 15-bit
counter which starts its count when the Target transaction is stored.
Target Abort.
This signal is asserted by the FPGA application to abort future
PCI Target and Configuration cycles. Once asserted, this signal needs to
remain asserted for a minimum of two
pciclk
cycles.
Target Retry.
This active-low signal is asserted by an FPGA application to
retry future PCI Target and Configuration cycles. Once asserted, this signal
needs to remain asserted for a minimum of two
pciclk
cycles.
Target Read Delayed Transaction
. Active-low signal which indicates to pro-
cesses certain future PCI Target accesses as delayed transactions. This
applies to memory reads, I/O reads, and I/O writes. Further description is pro-
vided in Table 3 for each PCI operation.
deltrn
must be asserted if
trburst-
pendn
is deasserted. Once asserted, this signal needs to remain asserted for
a minimum of two
pciclk
cycles and should not be changed while a current Tar-
get transaction is in progress.
—
t_ready
I
fclk
*
tstatecntr[3:0]
I
fclk
*
disctimerexpn
I
fclk
*
t_abort
O
pciclk
t_retryn
O
pciclk
deltrn
O
pciclk
PCI Bus Core Detailed Description
(continued)
Table 6. Embedded Core/FPGA Interface Signals
(continued)
* The source of the clock (
fclk1
or
fclk2
) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA352I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BAN256-DB | 制造商:Lattice Semiconductor Corporation 功能描述: |
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| OR3TP12-6PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
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