參數(shù)資料
型號： OR3TP12-6BA256
英文描述： Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 60/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA256
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
60
L Lucent Technologies Inc.
PCI Bus Core Target Controller Detailed Description
(continued)
For quad-port mode (Figure 19), the address and write data are transferred on the bus
twdata
in 16-bit segments.
The address will be split into two 16-bit components with the LSB being transferred first. If applicable, the dual-
address indication accompanies the address on
twdata[16]
, whereas for a single access on a 32-bit PCI bus
(
pci_64bit
= 0) the burst indication bit (
twdata[17]
) will be deasserted. Assuming a BAR size greater than 16 bits,
the address phase will require two clock cycles, and
twlastcycn
will be asserted on the final or MSB component of
the address.
The data phase will also require two clock cycles to transfer a single 32-bit write data word across the 16-bit bus.
twdataenn
can only be asserted while
tw_emptyn
is deasserted, indicating that write data is available in the write
data FIFOs. While
twdataenn
is asserted, the FPGA application will receive Target write data on bus
twdata
.
twlastcycn
will be deasserted for all 16-bit components of the write data phase, except for the final 16-bit compo-
nent, where it is asserted.
5-7354(F)
Figure 18. Target Write Single (FIFO Interface, Dual-Port)
1
T0
T1
T2
T3
0
4
0
CMD
ADRS
DATA
fclk
t_ready
tstatecntr
treqn
tcmd
datatofpga
fifo_sel
taenn
tw_emptyn
twdataenn
twlastcycn
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA256-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA256I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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