參數(shù)資料
型號(hào)： OR3TP12-6BA256
英文描述： Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁(yè)數(shù)： 20/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12-6BA256
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
20
L Lucent Technologies Inc.
PCI Bus Core Detailed Description
(continued)
Table 5. PCI Bus Pin Descriptions
(continued)
Symbol
I/O
Description
Interrupt Pins
intan
O
PCI Interrupt.
The OR3TP12 asserts this active-low signal when it requests an
interrupt from the PCI compliant interrupt controller.
64-Bit Bus Extension Pins
ad[63:32]
I/O
64-Bit Address and Data.
These signals provide the upper 32 bits of address and
data when in PCI 64-bit operation. During a 64-bit address phase (when using the
dual-address command (DAC) and when
req64n
is asserted), the upper 32-bit
address bits are transferred. During a data phase, the data is valid when
req64n
and
ack64n
are both asserted. Otherwise, these bits are 3-stated.
Byte Enables.
These are the upper four, active-low, bus command and byte
enables when in PCI 64-bit operation. During a 64-bit address phase (when using
the dual-address command (DAC) and when
req64n
is asserted), the bus com-
mand is transferred. During a data phase, these bits are the active-low byte enables
for data bits
ad[63:32]
. Otherwise, these bits are 3-stated.
Request 64-Bit Transfer.
This active-low signal is asserted by the current bus
Master to indicate that it desires to transfer data using 64 bits.
Acknowledge 64-Bit Transfer.
Within its decoded address space (DEVSELN
asserted), the Target drives this signal active-low indicating that it can perform
64-bit data transfers, in response to a received active-low
req64n
.
ack64n
has the
same timing as
devseln
in 32-bit transfers.
Upper Double-Word Parity
. The even parity bit that covers
ad[63:32]
and
c_ben[7:4]
.
par64n
is valid one clock after the initial address phase when
req64n
is asserted and the dual-address command (DAC) is indicated on
c_ben[3:0]
. It is
also valid the clock cycle after the second address phase of a DAC command when
req64n
is asserted. For data phases,
par64n
is stable and valid one clock after
irdyn
is asserted on a write transaction or
trdyn
is asserted on a read transaction.
Once
par64n
is valid, it remains valid until one clock after the completion of the cur-
rent data phase. On 64-bit PCI buses, the Master drives
par64n
for address and
write data phases; the Target drives
par64n
for read data phases.
c_ben[7:4]
I/O
req64n
I/O
ack64n
I/O
par64n
I/O
Hot Swap Function Pins
enumn
O
Enumeration.
Active-low signal that notifies the system host that the card has been
freshly inserted or is about to be extracted. The system host can then either install
(for insertion) or deactivate (for extraction) the card’s software driver to adjust for
the change in system configuration.
LED
. Active-low open-drain signal that drives a external blue LED, indicating that
removal of the card is permitted. This signal is asserted low whenever the LED
ON/
OFF (LOO) bit in the hot swap control and status register (HSSCR) is asserted
high.
Eject Switch.
Active-high signal that indicates that the card’s ejector handle is
unseated. This signals that the operator has freshly inserted the card, or will extract
the card when the blue LED illuminates. If not used, tie high or low.
PCI Bus Signaling Environment Voltage.
This input indicates to the PCI bus core
the signaling environment being employed on the PCI bus. The input is tied to the
appropriate voltage supply (either 5.0 V or 3.3 V).
ledn
O
ejectsw
I
vio
I
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA256-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA256I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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