參數(shù)資料
型號(hào)： OR3TP12-6BA256
英文描述： Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
中文描述： 用戶(hù)可編程ASIC的特殊功能
文件頁(yè)數(shù)： 54/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12-6BA256
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54
Lucent Technologies Inc.
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Target Controller Detailed
Description
(continued)
When the FPGA application reads the Target write
FIFO and empties it, the transaction status changes to
DWC (delayed write completion), and the next Target
I/O write that matches the stored command, address,
data, and byte enables will be disconnected with data,
completing the transaction and clearing the Target
address and Target write FIFOs.
Target Configuration Writes
Accesses of configuration space occur without any
involvement of the FPGA application. All configuration
space accesses are disconnected with data on the first
data word and are thus restricted from bursting.
Target Write Wait-States
All Target write data is accepted with zero wait-states.
When a Target memory write operation fills the Target
write FIFO, future response depends on signal
twburstpendn
. If it is deasserted, the Target will gen-
erate a disconnect without data on the next data cycle.
If it is asserted, the Target will insert up to eight wait-
states and then disconnect without data if the FIFO
remains full. Target I/O operations cannot fill the FIFO
because they do not burst, disconnecting with data on
the first Dword.
Command/Address Setup
When the Target has accepted a PCI Target transac-
tion, it will inform the FPGA application by asserting the
signal
treqn
. The FPGA application can then transfer
the PCI start address, Target command word, and data
in the specific order prescribed in Table 20 through
Table 23, for the operational mode (quad- and dual-
port). The address data is transferred via bus
twdata
(quad-port mode) or
datatofpga
(dual-port mode with
fifo_sel
= 1) when
taenn
is asserted.
taenn
should
only be asserted when
treqn
is active and
t_ready
is
active. The command/address phase ends with the
assertion of
twlastcycn
. The Target command word
(PCI bus command) and decoded BAR register are
transferred on the separate buses,
tcmd
and
bar
respectively, and are valid when
treqn
is active.
The number of cycles necessary to send the Target
address can vary. The Target FIFO interface will ana-
lyze the size of the decoded BAR and perform the min-
imal number of cycles to completely transfer the page
of the address. For example, if the BAR is 256K in size,
only the lower 18 bits of address is required by the
FPGA application. This will result in one clock address
transfer for dual-port (32-bits) and two for the quad-port
(16-bits).
Accompanying the address data during the assertion of
taenn
, is information on the current Target transaction
(Table 18). Dual-address or 64-bit address is indicated
during the address phase by
twdata[16]
(quad-port) or
datatofpgax[0]
(dual-port with
fifo_sel
= 1) being
asserted. If the current transaction is a burst,
twdata[17]
(quad-port) or
datatofpgax[1]
(dual-port
with
fifo_sel
= 1) will be asserted.
All burst transactions (burst indication bit active) and
64-bit agents (
pci_64bit
= 1) will have the Target data
aligned on a 64-bit address boundary (
ad2
= 0), even if
the PCI start address starts on a 32-bit address with
ad2
= 1. If the burst transaction on the PCI bus starts
on a odd 32-bit address boundary (
ad2
= 1), the data
phase start address will be on a 64-bit address bound-
ary (
ad2
= 0). Likewise, the data phase will also end on
a 64-bit address boundary, therefore the number of
transfers between the Target FIFO interface and the
FPGA application will always be even for burst transac-
tions
and 64-bit agents (
PCI_64bit
= 1).
Table 18. Bit Destinations for Target Command/Address Phase
* Refer to PCI Specification 2.2 Section 3.1.
Bits
Name
Description
Quad-Port
Dual-Port
Target Address Word (PCI Core
→
FPGA)
17
BI
16
DA
15:0
Adrs
Target Command Word (PCI Core
→
FPGA)
3:0
Cmd
Burst Indication
Dual-Address Indication
Address
twdata[17]
twdata[16]
twdata[15:0]
datatofpgax[1]
datatofpgax[0]
datatofpga[31:0]
PCI Command Code*
tcmd[3:0]
tcmd[3:0]
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA256-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA256I 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:User Programmable Special Function ASIC
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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