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| 型號(hào)： | OR3TP12-6BA256 |
| 英文描述： | Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁(yè)數(shù)： | 104/128頁(yè) |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12-6BA256 |
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
104
L Lucent Technologies Inc.
Table 41. FPGA Common-Function Pin Descriptions
(continued)
Symbol
I/O
Description
Special-Purpose Pins
(continued)
MPI_IRQ
O
I/O
O
I/O
O
MPI active-low interrupt request output.
If the MPI is not in use, this is a user-programmable I/O.
PowerPC mode MPI burst inhibit output.
If the MPI is not in use, this is a user-programmable I/O.
In PowerPCmode MPI operation, this is the active-high transfer acknowledge (TA) out-
put. For i960MPI operation, it is the active-low ready/record (RDYRCV) output.
If the MPI is not in use, this is a user-programmable I/O.
In PowerPCmode MPI operation, this is the active-low write/ active-high read control
signals. For i960operation, it is the active-high write/active-low read control signal.
If the MPI is not in use, this is a user-programmable I/O.
This is the clock used for the synchronous MPI interface. For PowerPC it is the CLK-
OUT signal. For i960 it is the system clock that is chosen for the i960 external bus inter-
face.
If the MPI is not in use, this is a user-programmable I/O.
For PowerPCoperation, these are the PowerPCaddress inputs. The address bit map-
ping (in PowerPCFPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/A[3], A[27]/
A[4]. Note that A[27]/A[4] is the MSB of the address. The A[4:2] inputs are not used in
i960 MPI mode.
If the MPI is not in use, this is a user-programmable I/O.
MPI_BI
MPI_ACK
MPI_RW
I
I/O
I
MPI_CLK
I/O
I
A[4:0]
I/O
I
A[1:0]/MPI_BE[1:0]
For i960 operation, MPI_BE[1:0] provide the i960byte enable signals,
be[1:0]
, that are
used as address bits A[1:0] in i960byte-wide operation.
During Master parallel, peripheral, and slave parallel configuration modes, D[7:0]
receive configuration data, and each pin has a pull-up enabled. During serial configura-
tion modes, D0 is the DIN input. D[7:0] are also the data pins for PowerPC microproces-
sor mode and the address/data pins for i960microprocessor mode.
After configuration, the pins are user-programmable I/O pins.*
During slave serial or Master serial configuration modes, DIN accepts serial configura-
tion data synchronous with CCLK. During parallel configuration modes, DIN is the D0
input. During configuration, a pull-up is enabled.
After configuration, this pin is a user-programmable I/O pin.*
During configuration, DOUT is the serial data output that can drive the DIN of daisy-
chained slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.
After configuration, DOUT is a user-programmable I/O pin.*
D[7:0]
I
I/O
I
DIN
I/O
O
DOUT
I/O
* The ORCASeries 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
Pin Information
(continued)
相關(guān)PDF資料 |
PDF描述 |
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| OR3TP12-6BA256I | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE |
| OR3TP12-6BA352 | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE |
| OR3TP12-6BA352I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
| OR3TP12-6PS240I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BA256-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA256I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BA256I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA352 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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