參數(shù)資料
型號： OR3TP12-6BA256
英文描述： Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 32/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA256
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
32
L Lucent Technologies Inc.
Subsystem Vendor ID
Subsystem ID
Minimum Grant (Min_Gnt)
Maximum Latency (Max_Lat)
Port Mode
I/O Mode
Master FIFO Interface Clock
Target FIFO Interface Clock
Target Address Comparator
0x2C—0x2D
0x2E—0x2F
0x3E
0x3F
Any 16-bit value.
Any 16-bit value.
Any 8-bit value.
Any 8-bit value.
Dual-port or quad-port.
Fast or slew-limited PCI output buffers.
fclk1
or
fclk2
.
fclk1
or
fclk2
.
Enabled or disabled; when enabled, the Target FIFO
interface will not transfer the MSB of the Target
address to the FPGA application, if it matches the
value of the previous transferred address. For dual-
port, the MSB will cover bits [64:32], whereas for
quad-port, the MSB represents bits [64:17]. If dis-
abled, the FPGA application will receive the address
covering the decoded BAR space.
Normal (16) or extended (32): The number of wait-
states to insert on Target reads until valid data is
recognized in the Target read data FIFOs. If no data
is detected, the Target will disconnect. Note that
only normal initial latency complies with PCI Specifi-
cation 2.2, Section 3.5.1.1. Extended latency may
be specified in proprietary systems where additional
clocks are required to return the first data word.
Target Maximum Initial Latency
Description
Hex Address in PCI
Configuration
Space
Optional Settings
PCI Bus Core Detailed Description
(continued)
Table 8. PCI Bus Core Options Settable via FPGA Configuration RAM Bits
(continued)
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA256-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA256I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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