參數(shù)資料
型號(hào)： OR3T806PS240-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 484 CLBS, 116000 GATES, PQFP240
封裝： PLASTIC, SQFP2-240
文件頁(yè)數(shù)： 90/203頁(yè)
文件大?。?/td> 1368K
代理商： OR3T806PS240-DB
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18
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Data is written to the write data, write address, and
write enable registers on the active edge of the clock,
but data is not written into the RAM until the next clock
edge one-half cycle later. The read port is actually
asynchronous, providing the user with read data very
quickly after setting the read address, but timing is also
provided so that the read port may be treated as fully
synchronous for write then read applications. If the
read and write address lines are tied together (main-
taining MSB to MSB, etc.), then the dual-port RAM
operates as a synchronous single-port RAM. If the
write enable is disabled, and an initial memory contents
is provided at conguration time, the memory acts as a
ROM (the write data and write address ports and write
port enables are not used).
Wider memories can be created by operating two or
more memory mode PFUs in parallel, all with the same
address and control signals, but each with a different
nibble of data. To increase memory word depth above
32, two or more PLCs can be used. Figure 10 shows a
128 x 8 dual-port RAM that is implemented in eight
PLCs. This gure demonstrates data path width expan-
sion by placing two memories in parallel to achieve an
8-bit data path. Depth expansion is applied to achieve
128 words deep using the 32-word deep PFU memo-
ries. In addition to the PFU in each PLC, the SLIC
(described in the next section) in each PLC is used for
read address decodes and 3-state drivers. The 128 x 8
RAM shown could be made to operate as a single-port
RAM by tying (bit-for-bit) the read and write addresses.
To achieve depth expansion, one or two of the write
address bits (generally the MSBs) are routed to the
write port enables as in Figure 10. For 2 bits, the bits
select which 32-word bank of RAM of the four available
from a decode of two WPE inputs is to be written. Simi-
larly, 2 bits of the read address are decoded in the
SLIC and are used to control the 3-state buffers
through which the read data passes. The write data bus
is common, with separate nibbles for width expansion,
across all PLCs, and the read data bus is common
(again, with separate nibbles) to all PLCs at the output
of the 3-state buffers.
Figure 10 also shows a new optional capability to pro-
vide a read enable for RAMs/ROMs in Series 3 using
the SLIC cell. The read enable will 3-state the read
data bus when inactive, allowing the write data and
read data buses to be tied together if desired.
Figure 10. Memory Mode Expansion Example—128 x 8 RAM
5-5749(F)
RD[7:0]
WE
WA[6:0]
RA[6:0]
CLK
WA
RA
WPE0
WPE1
WE
WD[7:4]
5
4
PLC
8
WD[7:0]
8
7
WA
RA
WPE0
WPE1
WE
RD[3:0]
WD[3:0]
5
4
PLC
RD[7:4]
WA
RA
WPE0
WPE1
WE
WD[7:4]
5
4
PLC
WA
RA
WPE0
WPE1
WE
RD[3:0]
WD[3:0]
5
4
PLC
RD[7:4]
RE
4
PFU
SLIC
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料
PDF描述
OR3T807PS240-DB FPGA, 484 CLBS, 116000 GATES, PQFP240
OR3T55-4BA256I FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256
OR3T55-4BA256 FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256
OR3T55-4BA352I FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA352
OR3T55-4BA352 FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA352
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3T80-6PS240I 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays
OR3T806PS240I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3872 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3T806S208-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use LatticeEC RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3T806S208I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use LatticeEC RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3T80-7BA352 制造商:Lattice Semiconductor Corporation 功能描述:Field-Programmable Gate Array, 484 Cell, 352 Pin, Plastic, BGA
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