參數(shù)資料
型號(hào)： OR3T806PS240-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 484 CLBS, 116000 GATES, PQFP240
封裝： PLASTIC, SQFP2-240
文件頁(yè)數(shù)： 142/203頁(yè)
文件大?。?/td> 1368K
代理商： OR3T806PS240-DB
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Lattice Semiconductor
43
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
PIC Architectural Description
The PIC architecture as seen in ispLEVER is shown in
Figure 27. The gure is the left PIC of a PIC pair on the
top edge of a Series 3 array. Both PICs in a pair are
similar, with the differences mainly lying in the connec-
tions between the PIC switching segments (pSW), the
IN2 connections across PIC boundaries, and the sys-
tem clock spine driver residing in only one PIC of a pair.
A
. This is a programmable input/output (PIO). There
are four PIOs per PIC. The PIOs contain the PIC
logic and I/O buffers.
B
. This is the PIC output switching block. It connects
the PIC switching segments and local clock lines to
the PIO output and control signals.
C
. This is the system clock spine switching block and
buffer. There is only one system clock spine per pair
of PICs. Its inputs can come from the PIC switching
segments or any of the eight PIO inputs in a PIC
pair.
D
. PIC switching segments (pSW). These routing seg-
ments are used to interconnect routing resources
within the PIC and to a lesser degree, between
PICs.
E
. px1 routing segments. The PIC x1 routing segments
traverse one PIC and break at a CIP in the middle of
each PIC.
F
. px2 routing segments. The PICs have routing that
traverses two PICs between breaks. The breaks are
staggered among the ve px2 segments.
G
. px5 routing segments. Each of the ten PIC x5 rout-
ing segments traverses ve PICs in between breaks
at a CIP. Two px5 segments break in each PIC.
H
. pxH routing segments. The eight PIC xH routing
segments traverse half of the array and break at
CIPs in the interquad routing region that is in the
middle of the array.
I
.
(Not used intentionally for clarity.)
J
. pxL routing segments. The PIC long lines run the
entire length of the side of the array.
K
. x5 routing segments from the adjacent PLC routing.
L
. xL routing segments from the adjacent PLC routing.
M
. x1 routing segments from the adjacent PLC routing.
N
. Switching segments from the adjacent PLC routing.
O
. xH routing segments from the adjacent PLC routing.
P
. BIDI routing segments from the adjacent PLC rout-
ing.
Q
. These are the IN2 routing segments. There is one
IN2 line from each PIO, and all eight IN2 lines from
each PIC pair are present in both PICs of a pair.
R
. These CIPs connect the IN1 and IN2 routing seg-
ments from the PIOs to the PIC switching seg-
ments.
S
. These CIPs break the PIC switching segments at
the interface between a PIC pair.
T
. These CIPs connect adjacent PLC routing
resources to the PIC switching segments.
U
. These CIPs connect inter-PIC routing with the PIC
switching segments.
V
. These CIPs break the px1, px2, and px5 routing at
the middle of a PIC. The px2 and px5 CIP place-
ment varies depending on the PLC.
W
. These mutually exclusive buffers can drive one long
line signal onto a PIC local clock routing segment.
X
. These mutually exclusive buffers can select a
source from one of the local system clock routes to
drive the PIO 3-state control signal.
Y
. These are the four local system clock routing seg-
ments. Two come from connections within the PIC,
one from the other PIC in the pair, and one from the
adjacent PLC.
Z
. These mutually exclusive buffers allow a signal on
the PIC switching segments to be routed to a sys-
tem clock spine or to a PIO system clock.
AA
. ExpressCLK routing line.
AB
. System clock spine.
AC
. These various groups of CIPs connect routing
resources from the adjacent PLC to the inter-PIC
routing resources.
AD
. These buffers provide connectivity between the
PLC xL (xH) lines and the PIC xL (xH) lines or
connectivity between one of the IN2 routing seg-
ments and the PIC and/or PLC xL (xH) routing
segments.
AE
. These mutually exclusive buffers and CIPs provide
connectivity to the PLC xL and xH lines from one
of the IN2 input segments.
AF
. These buffers allow the IN2 signals to drive onto
the BIDI routing of the adjacent PLC, or the BIDI
routing of the adjacent PLC, and the PIC switching
segments and/or PIC half lines may be connected.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料
PDF描述
OR3T807PS240-DB FPGA, 484 CLBS, 116000 GATES, PQFP240
OR3T55-4BA256I FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256
OR3T55-4BA256 FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256
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OR3T806PS240I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 3872 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3T806S208-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 Use LatticeEC RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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OR3T80-7BA352 制造商:Lattice Semiconductor Corporation 功能描述:Field-Programmable Gate Array, 484 Cell, 352 Pin, Plastic, BGA
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