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參數(shù)資料
| 型號(hào)： | OR3T807PS240-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 116000 GATES, PQFP240 |
| 封裝： | PLASTIC, SQFP2-240 |
| 文件頁(yè)數(shù)： | 1/203頁(yè) |
| 文件大小： | 1368K |
| 代理商： | OR3T807PS240-DB |
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Data Sheet
November 2006
ORCA Series 3C and 3T
Field-Programmable Gate Arrays
Features
■ High-performance, cost-effective, 0.35 m (OR3C) and
0.3 m (OR3T) 4-level metal technology, (4- or 5-input
look-up table delay of 1.1 ns with -7 speed grade in
0.3 m).
■ Same basic architecture as lower-voltage, advanced
process technology Series 3 architectures. (See
ORCA
Series 3L FPGA documentation.)
■ Up to 186,000 usable gates.
■ Up to 342 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
■ Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
■ Twin-quad programmable function unit (PFU) architec-
ture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
■ Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be dis-
abled per PFU.
■ Flexible input structure (FINS) of the PFUs provides a
routability enhancement for LUTs with shared inputs and
the logic exibility of LUTs with independent inputs.
■ Fast-carry logic and routing to adjacent PFUs for nibble-,
byte-wide, or longer arithmetic functions, with the option
to register the PFU carry-out.
■ Softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
■ Supplemental logic and interconnect cell (SLIC) pro-
vides 3-statable buffers, up to 10-bit decoder, and
PAL*-
like AND-OR with optional INVERT in each programma-
ble logic cell (PLC), with over 50% speed improvement
typical.
■ Abundant hierarchical routing resources based on rout-
ing two data nibbles and two control lines per set provide
for faster place and route implementations and less rout-
ing delay.
■ TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
■ Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source.
■ Built-in boundary scan (IEEE
1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
■ Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
■ Up to four ExpressCLK inputs allow extremely fast clock-
ing of signals on- and off-chip plus access to internal
general clock routing.
■ StopCLK feature to glitchlessly stop/start ExpressCLKs
independently by user command.
■ Programmable I/O (PIO) has:
— Fast-capture input latch and input ip-op (FF) latch
for reduced input setup time and zero hold time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and
PAL-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain dive capability
— Capability to register 3-state enable signal.
■ Baseline FPGA family used in Series 3+ FPSCs (eld
programmable system chips) which combine FPGA logic
and standard cell logic on one device.
*
PAL is a trademark of Advanced Micro Devices, Inc.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1.
ORCA Series 3 (3C and 3T) FPGAs
The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
Device
System
Gates
LUTs
Registers
Max User RAM
Max User
I/Os
Array Size
Process
Technology
OR3T20
36K
1152
1872
18K
192
12 x 12
0.3 m/4 LM
OR3T30
48K
1568
2436
25K
221
14 x 14
0.3 m/4 LM
OR3T55
80K
2592
3780
42K
288
18 x 18
0.3 m/4 LM
OR3C/3T80
116K
3872
5412
62K
342
22 x 22
0.3 m/4 LM
OR3T125
186K
6272
8400
100K
342
28 x 28
0.3 m/4 LM
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T55-4BA256I | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256 |
| OR3T55-4BA256 | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256 |
| OR3T55-4BA352I | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA352 |
| OR3T55-4BA352 | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA352 |
| OR3T80-4BA352I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA352 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T80-7PS240I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T807S208-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use LatticeEC RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| OR3TP12-6BA256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BA256-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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