參數(shù)資料
型號(hào)： OR3T806PS240-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 484 CLBS, 116000 GATES, PQFP240
封裝： PLASTIC, SQFP2-240
文件頁(yè)數(shù)： 200/203頁(yè)
文件大?。?/td> 1368K
代理商： OR3T806PS240-DB
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96
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
FPGA Conguration Modes (continued)
Daisy-Chaining
Multiple FPGAs can be congured by using a daisy-
chain of the FPGAs. Daisy-chaining uses a lead FPGA
and one or more FPGAs congured in slave serial
mode. The lead FPGA can be congured in any mode
except slave parallel mode. (Daisy-chaining is available
with the boundary-scan ram_w instruction discussed
later.)
All daisy-chained FPGAs are connected in series.
Each FPGA reads and shifts the preamble and length
count in on positive CCLK and out on negative CCLK
edges.
An upstream FPGA that has received the preamble
and length count outputs a high on DOUT until it has
received the appropriate number of data frames so that
downstream FPGAs do not receive frame start bit
pairs. After loading and retransmitting the preamble
and length count to a daisy-chain of slave devices, the
lead device loads its conguration data frames.
The loading of conguration data continues after the
lead device has received its conguration data if its
internal frame bit counter has not reached the length
count. When the conguration RAM is full and the num-
ber of bits received is less than the length count eld,
the FPGA shifts any additional data out on DOUT.
The conguration data is read into DIN of slave devices
on the positive edge of CCLK, and shifted out DOUT
on the negative edge of CCLK. Figure 63 shows the
connections for loading multiple FPGAs in a daisy-
chain conguration.
The generation of CCLK for the daisy-chained devices
that are in slave serial mode differs depending on the
conguration mode of the lead device. A master paral-
lel mode device uses its internal timing generator to
produce an internal CCLK at eight times its memory
address rate (RCLK). The asynchronous peripheral
mode device outputs eight CCLKs for each write cycle.
If the lead device is congured in slave mode, CCLK
must be routed to the lead device and to all of the
daisy-chained devices.
5-4488(F
Figure 63. Daisy-Chain Conguration Schematic
As seen in Figure 63, the INIT pins for all of the FPGAs are connected together. This is required to guarantee that
powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected
together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be
required, depending upon the start-up sequence desired.
VDD
EPROM
PROGRAM
D[7:0]
OE
CE
A[17:0]
D[7:0]
DONE
M2
M1
M0
DONE
HDC
LDC
RCLK
CCLK
DOUT
DIN
DOUT
DIN
CCLK
DONE
DOUT
INIT
CCLK
VDD
VDD OR
GND
PRGM
M2
M1
M0
PRGM
M2
M1
M0
VDD
HDC
LDC
RCLK
HDC
LDC
RCLK
VDD
ORCA
SERIES
FPGA
SLAVE #2
ORCA
SERIES
FPGA
MASTER
ORCA
SERIES
FPGA
SLAVE #1
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料
PDF描述
OR3T807PS240-DB FPGA, 484 CLBS, 116000 GATES, PQFP240
OR3T55-4BA256I FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256
OR3T55-4BA256 FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256
OR3T55-4BA352I FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA352
OR3T55-4BA352 FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA352
相關(guān)代理商/技術(shù)參數(shù)
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OR3T806S208I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use LatticeEC RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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