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| 型號(hào)： | OR3C804BA352-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 116000 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁(yè)數(shù)： | 196/203頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3C804BA352-DB |
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92
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
FPGA Conguration Modes (continued)
Asynchronous Peripheral Mode
Figure 56 shows the connections needed for the asyn-
chronous peripheral mode. In this mode, the FPGA
system interface is similar to that of a microprocessor-
peripheral interface. The microprocessor generates the
control signals to write an 8-bit byte into the FPGA. The
FPGA control inputs include active-low CS0 and active-
high CS1 chip selects and WR and RD inputs. The chip
selects can be cycled or maintained at a static level
during the conguration cycle. Each byte of data is writ-
ten into the FPGA’s D[7:0] input pins. D[7:0] of the
FPGA can be connected to D[7:0] of the microproces-
sor only if a standard prom le format is used. If a .bit
or .rbt le is used from ispLEVER, then the user must
mirror the bytes in the .bit or .rbt le OR leave the .bit or
.rbt le unchanged and connect D[7:0] of the FPGA to
D[0:7] of the microprocessor.
The FPGA provides an RDY/BUSY status output to indi-
cate that another byte can be loaded. A low on RDY/
BUSY
indicates that the double-buffered hold/shift reg-
isters are not ready to receive data, and this pin must
be monitored to go high before another byte of data
can be written. The shortest time RDY/BUSY is low
occurs when a byte is loaded into the hold register and
the shift register is empty, in which case the byte is
immediately transferred to the shift register. The long-
est time for RDY/BUSY to remain low occurs when a
byte is loaded into the holding register and the shift
register has just started shifting conguration data into
conguration RAM.
The RDY/BUSY status is also available on the D7 pin by
enabling the chip selects, setting WR high, and apply-
ing RD low, where the RD input provides an output
enable for the D7 pin when RD is low. The D[6:0] pins
are not enabled to drive when RD is low and, therefore,
only act as input pins in asynchronous peripheral
mode. Optionally, the user can ignore the RDY/BUSY
status and simply wait until the maximum time it would
take for the RDY/BUSY line to go high, indicating the
FPGA is ready for more data, before writing the next
data byte.
Figure 56. Asynchronous Peripheral Conguration
Microprocessor Interface
(MPI) Mode
The built-in MPI in Series 3 FPGAs is designed for use
in conguring the FPGA. Figure 57 and Figure 58 show
the glueless interface for FPGA conguration and read-
back from the
PowerPC and i960 processors, respec-
tively. When enabled by the mode pins, the MPI
handles all conguration/readback control and hand-
shaking with the host processor. For single FPGA con-
guration, the host sets the conguration control
register PRGM bit to zero then back to a one and, after
reading that the INIT signal is high in the MPI status
register, transfers data 8 bits at a time to the FPGA’s
D[7:0] input pins.
If conguring multiple FPGAs through daisy-chain
operation is desired, the MP_DAISY bit must be set in
the conguration control register of the MPI. Because
of the latency involved in a daisy-chain conguration,
the MP_HOLD_BUS bit may be set to zero rather than
one for daisy-chain operation. This allows the MPI to
acknowledge the data transfer before the conguration
information has been serialized and transferred on the
FPGA daisy-chain. The early acknowledgment frees
the host processor to perform other system tasks. Con-
guring with the MP_HOLD_BUS bit at zero requires
that the host microprocessor poll the RDY/BUSY bit of
the MPI status register and/or use the MPI interrupt
capability to conrm the readiness of the MPI for more
conguration data.
MICRO-
PROCESSOR
D[7:0]
CS1
M2
M1
M0
HDC
ORCA
SERIES
FPGA
8
LDC
VDD
DONE
CS0
DOUT
CCLK
TO DAISY-
CHAINED
DEVICES
BUS
CONTROLLER
ADDRESS
DECODE LOGIC
RD
WR
RDY/BUSY
INIT
PRGM
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3C804PS208-DB | FPGA, 484 CLBS, 116000 GATES, PQFP208 |
| OR3T1256PS208I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| OR3T1256PS240-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1256PS240I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1257PS208-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C80-4BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804BA352I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-4BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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