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參數(shù)資料
| 型號： | OR3C804BA352-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 116000 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 187/203頁 |
| 文件大小： | 1368K |
| 代理商： | OR3C804BA352-DB |
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84
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
FPGA States of Operation (continued)
If conguration has begun, an assertion of RESET or
PRGM
initiates an abort, returning the FPGA to the ini-
tialization state. The PRGM and RESET pins must be
pulled back high before the FPGA will enter the cong-
uration state. During the start-up and operating states,
only the assertion of PRGM causes a reconguration.
In the master conguration modes, the FPGA is the
source of conguration clock (CCLK). In this mode, the
initialization state is extended to ensure that, in daisy-
chain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an addi-
tional six internal clock cycles after INIT goes high.
When conguration is initiated, a counter in the FPGA
is set to 0 and begins to count conguration clock
cycles applied to the FPGA. As each conguration data
frame is supplied to the FPGA, it is internally assem-
bled into data words. Each data word is loaded into the
internal conguration memory. The conguration load-
ing process is complete when the internal length count
equals the loaded length count in the length count eld,
and the required end of conguration frame is written.
All OR3Cxx I/Os operate as TTL inputs during congu-
ration (OR3Txxx I/Os are CMOS-only). All I/Os that are
not used during the conguration process are
3-stated with internal pull-ups.
Warning: During conguration, all OR3Txxx inputs
have internal pull-ups enabled. If these inputs are
driven to 5V, they will draw substantial current (
5 ma).
This is due to the fact that the inputs are pulled up to
3V.
During conguration, the PIC and PLC latches/FFs are
held set/reset and the internal BIDI buffers are 3-
stated. The combinatorial logic begins to function as
the FPGA is congured. Figure 50 shows the general
waveform of the initialization, conguration, and start-
up states.
Conguration
The
ORCA Series FPGA functionality is determined by
the state of internal conguration RAM. This congura-
tion RAM can be loaded in a number of different
modes. In these conguration modes, the FPGA can
act as a master or a slave of other devices in the sys-
tem. The decision as to which conguration mode to
use is a system design issue. Conguration is dis-
cussed in detail, including the conguration data format
and the conguration modes used to load the congu-
ration data in the FPGA, following a description of the
start-up state.
5-4482(F)
Figure 50. Initialization/Configuration/Start-Up Waveforms
VDD
M[3:0]
CCLK
HDC
LDC
DONE
USER I/O
INTERNAL
RESET
(gsrn)
CONFIGURATION
OPERATION
INITIALIZATION
START-UP
RESET
PRGM
INIT
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C80-4BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804BA352I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-4BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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