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參數(shù)資料
| 型號(hào)： | OR3C804BA352-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 116000 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁(yè)數(shù)： | 158/203頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3C804BA352-DB |
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58
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Special Function Blocks (continued)
ORCA Boundary-Scan Circuitry
The
ORCA Series boundary-scan circuitry includes a
test access port controller (TAPC), instruction register
(IR), boundary-scan register (BSR), and bypass regis-
ter. It also includes circuitry to support the four pre-
dened instructions.
Figure 38 shows a functional diagram of the boundary-
scan circuitry that is implemented in the
ORCA Series.
The input pins’ (TMS, TCK, and TDI) locations vary
depending on the part, and the output pin is the dedi-
cated TDO/RD_DATA output pad. Test data in (TDI) is
the serial input data. Test mode select (TMS) controls
the boundary-scan test access port controller (TAPC).
Test clock (TCK) is the test clock on the board.
The BSR is a series connection of boundary-scan cells
(BSCs) around the periphery of the IC. Each I/O pad on
the FPGA, except for CCLK, DONE, and the boundary-
scan pins (TCK, TDI, TMS, and TDO), is included in the
BSR. The rst BSC in the BSR (connected to TDI) is
located in the rst PIC I/O pad on the left of the top side
of the FPGA (PTA PIC). The BSR proceeds clockwise
around the top, right, bottom, and left sides of the array.
The last BSC in the BSR (connected to TDO) is located
on the top of the left side of the array (PL1D).
The bypass instruction uses a single FF, which resyn-
chronizes test data that is not part of the current scan
operation. In a bypass instruction, test data received on
TDI is shifted out of the bypass register to TDO. Since
the BSR (which requires a two FF delay for each pad)
is bypassed, test throughput is increased when devices
that are not part of a test operation are bypassed.
The boundary-scan logic is enabled before and during
conguration. After conguration, a conguration
option determines whether or not boundary-scan logic
is used.
The 32-bit boundary-scan identication register con-
tains the manufacturer’s ID number, unique part num-
ber, and version (as described earlier). The
identication register is the default source for data on
TDO after RESET if the TAP controller selects the shift-
data-register (SHIFT-DR) instruction. If boundary scan
is not used, TMS, TDI, and TCK become user I/Os, and
TDO is 3-stated or used in the readback operation.
An optional USERCODE is available if the boundary-
scan PSR1 instruction is not used. The selection
between PSR1 and USERCODE is a conguration
option and can be performed in ispLEVER. The USER-
CODE is an 11-bit value that the user can set during
device conguration and can be written to and read
from the FPGA via the boundary-scan logic. The
USERCODE value replaces the manufacturer eld of
the boundary-scan ID code when the USERCODE
instruction is issued, allowing users to have congured
devices identied in a user-dened manner. The manu-
facturer ID eld remains available when the IDCODE
instruction is issued.
5-5768(F)
Figure 38.
ORCA Series Boundary-Scan Circuitry Functional Diagram
TAP
CONTROLLER
TMS
TCK
BOUNDARY-SCAN REGISTER
PSR2 REGISTER (PLCs)
BYPASS REGISTER
DATA
MUX
INSTRUCTION DECODER
INSTRUCTION REGISTER
M
U
X
RESET
CLOCK IR
SHIFT-IR
UPDATE-IR
PUR
TDO
SELECT
ENABLE
RESET
CLOCK DR
SHIFT-DR
UPDATE-DR
TDI
DATA REGISTERS
PSR1 REGISTER (PLCs)
CONFIGURATION REGISTER
(RAM_R, RAM_W)
PRGM
I/O BUFFERS
VDD
IDCODE REGISTER
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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| OR3C804PS208-DB | FPGA, 484 CLBS, 116000 GATES, PQFP208 |
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| OR3T1256PS240-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C80-4BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804BA352I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-4BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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