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參數(shù)資料
| 型號(hào)： | OR3C804BA352-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 116000 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁(yè)數(shù)： | 134/203頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3C804BA352-DB |
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36
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
Inputs
As outlined earlier in Table 9, there are six major
options on the PIO inputs that can be selected in the
ispLEVER tools. For OR3Cxx devices, the inputs and
bidirectional buffers can be congured as either TTL or
CMOS compatible. OR3Txxx devices support CMOS
levels only for input or bidirectional buffers, have 5 V
tolerant I/Os as previously explained, but can optionally
be selected on a pin-by-pin basis to be PCI bus 3.3 V
signaling compliant (PCI bus 5 V signaling compliance
occurs in 5 V tolerant operation). The default buffer
upon powerup for the unused sites is 5 V tolerant/5 V
PCI compliant. Consult the
ORCA macro library, Series
3 I/O cells, for the appropriate buffers. Inputs may have
a pull-up or pull-down resistor selected on an input for
signal stabilization and power management. Input sig-
nals in a PIO can be passed to PIC routing on any of
three paths, two general signal paths into PIC routing,
and/or a fast route into the clock routing system.
There is also a programmable delay available on the
input. When enabled, this delay affects the IN1 and IN2
signals of each PIO, but not the clock input. The delay
allows any signal to have a guaranteed zero hold time
when input. This feature is discussed subsequently.
Inputs should have transition times of less than 500 ns
and should not be left oating. If any pin is not used, it
is 3-stated with an internal pull-up resistor enabled
automatically after conguration.
Warning: During conguration, all OR3Txxx inputs
have internal pull-ups enabled. If these inputs are
driven to 5 V, they will draw substantial current
(
5 mA). This is due to the fact that the inputs are
pulled up to 3 V.
Floating inputs increase power consumption, produce
oscillations, and increase system noise. The OR3Cxx
inputs have a typical hysteresis of approximately 280
mV (200 mV for the OR3Txxx) to reduce sensitivity to
input noise. The PIC contains input circuitry which pro-
vides protection against latch-up and electrostatic dis-
charge.
The other features of the PIO inputs relate to the new
latch/FF structure in the input path. As shown in
Figure 23, the input is optionally passed to a register or
latch/register pair. These structures can operate in the
modes listed in Table 9. In latch mode, the input signal
is fed to a latch that is clocked by a system clock signal.
The clock may be inverted or noninverted from its
sense in the PIC routing. There is also a local set/reset
signal to the latch from the PIC routing. The senses of
these signals are also programmable as well as the
capability to enable or disable the global set/reset sig-
nal and select the set/reset priority. The same control
signals may also be used to control the input latch/FF
when it is congured as a FF instead of a latch, with the
addition of another control signal used as a clock
enable.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3C804PS208-DB | FPGA, 484 CLBS, 116000 GATES, PQFP208 |
| OR3T1256PS208I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| OR3T1256PS240-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1256PS240I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1257PS208-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C80-4BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804BA352I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-4BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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