參數(shù)資料
型號(hào): NRF9E5IC
廠商: Electronic Theatre Controls, Inc.
英文描述: 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC
中文描述: 433/868/915MHz RF收發(fā)器與8051兼容的嵌入式微控制器和4輸入,10位ADC
文件頁(yè)數(shù): 43/104頁(yè)
文件大?。?/td> 1436K
代理商: NRF9E5IC
PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone +4772898900 - Fax +4772898989
Revision: 1.1
Page 43 of 104
June 2004
13
SPI
nRF9E5 SPI is a simple single buffered master. The 3 data lines of the SPI bus (MISO,
SCK and MOSI) are multiplexed (by writing to register SPI_CTRL) between the GPIO
pins (lower 3 bits of P1) and the RF transceiver and AD converter subsystems. The SPI
hardware does not generate any chip select signal. The bootstrap loader uses EECSN
(GPIO P0.3) as chip select for the boot EEPROM. On-chip GPIO P2.3 is dedicated as
chip select for the RF transceiver and AD converter subsystems. GPIO pins from port 0
may be used as chip selects for other external SPI slaves.
The SPI hardware is controlled by SFR’s SPI_DATA (0xb2), SPI_CTRL (0xb3) and
SPICLK (0xb4) as explained in Table 33 below.
Addr
SFR
(hex)
B2
B3
R/W
#bit
Init
(hex)
Name
Function
R/W
R/W
8
2
0
0
SPI_DATA
SPI_CTRL
SPI data input/output
00 -> SPI not used no clock generated
01 -> SPI connected to port P1 (as for booting)
(see also Table 11 Port 1 (P1) functions)
10 -> SPI connected to the nRF905 transceiver
(see Table 15 P2 (RADIO) register )
Divider factor from CPU clock to SPI clock
0000: 1/2 of CPU clock frequency
0001: 1/2 of CPU clock frequency
0010: 1/4 of CPU clock frequency
0011: 1/8 of CPU clock frequency
0100: 1/16 of CPU clock frequency
0101: 1/32 of CPU clock frequency
0110: 1/64 of CPU clock frequency
other: 1/64 of CPU clock frequency
B4
R/W
4
0
SPICLK
Table 33 SPI control and data SFR-registers.
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