參數(shù)資料
型號： NRF9E5IC
廠商： Electronic Theatre Controls, Inc.
英文描述： 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC
中文描述： 433/868/915MHz RF收發(fā)器與8051兼容的嵌入式微控制器和4輸入，10位ADC
文件頁數(shù)： 15/104頁
文件大?。?/td> 1436K
代理商： NRF9E5IC
PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone +4772898900 - Fax +4772898989
Revision: 1.1
Page 15 of 104
June 2004
Port 0 is controlled by SFR-registers 0x80, 0x93, 0x94 and 0x95 listed in the table
below.
Addr
SFR
(hex)
R/W
#bit
Init
value
(hex)
FF
00
Name
Function
80
93
R/W
R/W
8
8
P0
P0_DRV
Port 0, pins P07 to P00
High drive strength for each bit of Port 0
0: Enable, 1: Disable
(See 6.2.1 below for a description)
Direction for each bit of Port 0
0: Output, 1: Input
Direction is overridden if alternate function is
selected for a pin.
Select alternate functions for each pin of P0, if
corresponding bit in P0_ALT is set, as listed in
Table 9 Port 0 (P0) functions.
94
R/W
8
FF
P0_DIR
95
R/W
8
00
P0_ALT
Table 10 Port 0 control and data SFR-registers.
6.2.1
High Current Drive Capability
Odd numbered bits will source high current when the corresponding bit in P0_DRV is
set, where as even number bits will sink high current when the corresponding bit in
P0_DRV is set.
6.3
Port 1 (P1 or SPI port)
The P1 port consists of 4 pins, one of which is a hardwired input. The primary function
of the P1 port (when SPI_CTRL is 01) is a SPI master port. The pin EECSN is used as a
chip select for the boot EEPROM, the GPIO bits in port P0 may be used as chip select(s)
for other SPI devices.
When not used as SPI port, P1_ALT.0 will force SCK (P1.0) to be the timer T2 input;
MOSI (P1.1) is now a GPIO. When P0_ALT.0 is 0, also SCK (P1.0) is a GPIO.
MISO (P1.2) is always an input. That is P1_DIR.2 and P1_ALT.2 are ignored.
EECSN (P1.3) is always a GPIO. It will be activated by the default boot loader after
reset and should be connected to the CSN of the boot flash.
SPI_CTRL != 01
P1_ALT.n = 0
Pin
SPI_CTRL = 01
P1_ALT.n = 1
P1_DIR.n = 0
P1.0
P1.1
P1.2
P1.3
P1_DIR.n = 1
P1.0
P1.1
P1.2
P1.3
SCK
MOSI
MISO
EECSN
SPI.clock
SPI.dataout
SPI.datain
P1.3
Out
Out
In
Out
T2
P1.1
P1.2
P1.3
In
I/O
2
In
I/O
2
In
In
In
In
Out
Out
In
Out
Table 11 Port 1 (P1) functions.
2
P1.1 and P1.3 are actually under control of P1_DIR.1 and P1_DIR.3 even when P1_ALT.1 or P1_ALT.3
are 1, since there are no alternate functions for these pins.
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