參數(shù)資料
型號(hào)： NANDB9R4N2BZBA5F
廠商： NUMONYX
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA149
封裝： 10 X 13.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-149
文件頁(yè)數(shù)： 19/52頁(yè)
文件大?。?/td> 1126K
代理商： NANDB9R4N2BZBA5F
Signal descriptions
NANDxxxxNx
2.6
Flash memory Read Enable (R)
The NAND flash memory Read Enable pin, R, controls the sequential data output during
read operations. The falling edge of R also increments the internal column address counter
by one.
2.7
Flash memory Write Enable (WF)
The NAND flash memory Write Enable input, WF, controls writing to the command interface,
input address, and data latches. Both addresses and data are latched on the rising edge of
Write Enable.
2.8
Flash memory Write Protect (WP)
The Write Protect pin is a NAND flash memory input that gives a hardware protection
against unwanted program or erase operations. When Write Protect is Low, VIL, the NAND
flash memory device does not accept any program or erase operations.
It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
2.9
Flash memory Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain NAND flash memory output that can be used
to identify if the P/E/R controller is currently active.
When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the
operation completes Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low then indicates that one or more of the
memories is busy.
2.10
Flash memory VDDF supply voltage
VDDF provides the power supply to the internal core of the NAND flash memory device. It is
the main power supply for all operations (read, program and erase).
2.11
LPSDRAM Address inputs (A0-Ax)
The A0-Ax address inputs are used by the LPSDRAM to select the row or column to be
made active. If A10 is High (set to ‘1’) during read or write, the read or write cycle operation
includes an auto precharge cycle. If A10 is Low (set to ‘0’) during read or write, the read or
write cycle does not include an auto precharge cycle.
2.12
LPSDRAM Bank Select Address inputs (BA0-BA1)
The BA0 and BA1 banks select address inputs are used by the LPSDRAM to select the
bank to be made active.
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