參數(shù)資料
型號: NAND512R3A2AZB6E
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 64M X 8 FLASH 1.8V PROM, 35 ns, PBGA55
封裝: 8 X 10 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-55
文件頁數(shù): 15/57頁
文件大小: 916K
代理商: NAND512R3A2AZB6E
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
22/57
Read Memory Array
Each operation to read the memory area starts
with a pointer operation as shown in the Pointer
Operations section. Once the area (main or spare)
has been selected using the Read A, Read B or
Read C commands four bus cycles (for 512Mb
and 1Gb devices) or three bus cycles (for 128Mb
and 256Mb devices) are required to input the ad-
dress (refer to Table 6.) of the data to be read.
The device defaults to Read A mode after power-
up or a Reset operation.
When reading the spare area addresses:
A0 to A3 (x8 devices)
A0 to A2 (x16 devices)
are used to set the start address of the spare area
while addresses:
A4 to A7 (x8 devices)
A3 to A7 (x16 devices)
are ignored.
Once the Read A or Read C commands have
been issued they do not need to be reissued for
subsequent read operations as the pointer re-
mains in the respective area. However, the Read
B command is effective for only one operation,
once an operation has been executed in Area B
the pointer returns automatically to Area A and so
another Read B command is required to start an-
other read operation in Area B.
Once a read command is issued three types of op-
erations are available: Random Read, Page Read
and Sequential Row Read.
Random Read. Each time the command is is-
sued the first read is Random Read.
Page Read. After the Random Read access the
page data is transferred to the Page Buffer in a
time of tWHBH (refer to Table 21. for value). Once
the transfer is complete the Ready/Busy signal
goes High. The data can then be read out sequen-
tially (from selected column address to last column
address) by pulsing the Read Enable signal.
Sequential Row Read. After the data in last col-
umn of the page is output, if the Read Enable sig-
nal is pulsed and Chip Enable remains Low then
the next page is automatically loaded into the
Page Buffer and the read operation continues. A
Sequential Row Read operation can only be used
to read within a block. If the block changes a new
read command must be issued.
Refer to Figure 15. and Figure 16. for details of Se-
quential Row Read operations.
To terminate a Sequential Row Read operation set
the Chip Enable signal to High for more than tEHEL.
Sequential Row Read is not available when the
Chip Enable Don't Care option is enabled.
相關(guān)PDF資料
PDF描述
NAND01GW3A0CZB1F 128M X 8 FLASH 3V PROM, 35 ns, PBGA63
NAND01GW3A2AN1 128M X 8 FLASH 3V PROM, 35 ns, PDSO48
NAND01GW3A2AZB1E 128M X 8 FLASH 3V PROM, 35 ns, PBGA63
NAND01GW3A0CZB1 128M X 8 FLASH 3V PROM, 35 ns, PBGA63
NAND01GW3A2BN6T 128M X 8 FLASH 3V PROM, 35 ns, PDSO48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND512R3A2BZA6E 功能描述:閃存 128Mbit-1Gbit 1.8/3V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
NAND512R3A2CZA6E 功能描述:IC FLASH 512MBIT 63VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步,DDR II 存儲容量:18M(1M x 18) 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA(13x15) 包裝:托盤 其它名稱:71P71804S200BQ
NAND512R3A2CZA6F 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 1.8V 512Mbit 64M x 8bit 15us 63-Pin VFBGA T/R
NAND512R3A2DDI6 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film
NAND512R3A2DZA6E 功能描述:IC FLASH 512MBIT 63VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C,2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR)